Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2001-03-07
2002-06-11
Elms, Richard (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S052000, C257S686000
Reexamination Certificate
active
06404662
ABSTRACT:
TECHNICAL FIELD
The present invention relates to methods and apparatus for achieving a stacked configuration of memory modules that conforms to a RAMBUS specification.
BACKGROUND OF THE INVENTION
Recent developments in Dynamic Random Access Memory (DRAM) design, as disclosed by RAMBUS, Inc. in U.S. Pat. No. 5,511,024, have resulted in substantially increased memory accessing speeds over fewer signal lines. By multiplexing data, address, and control signals, and providing circuitry for timing control, fewer signal lines connecting DRAM to a processor or memory controller are required. This substantially reduces the cost and increases the flexibility of implementing a signal channel bus on a printed circuit board. However, to achieve high memory accessing speed, the signal lines must have a very high bandwidth in comparison to former DRAM implementations. To achieve high bandwidth, tight control over the design of the printed circuit board is required.
A segment of a typical DRAM circuit layout is shown in FIG.
1
A. The controller is connected to the memory modules by a series of metal signal traces laid out on the printed circuit board. In
FIG. 1A
, only a few signal traces are shown. Typically, the DRAM will be connected to multiple traces as shown in FIG.
1
B. These traces carry the data, address and control signals. Also, means for connecting the circuit components to power and ground are provided. The signal traces will typically converge from the pins of the controller to form a series of substantially parallel lines connecting to the leads of the DRAMs. Multiple DRAMs may be connected in parallel as shown in FIG.
1
A. The controller selects the DRAM to be addressed using chip select signals. The controller may be connected to the DRAMs by way of a socket as shown. However, the socket may be omitted. Commonly the DRAMs are connected to a power plane and to a ground plane by vias, which are metallized holes drilled in the printed circuit board to connect leads to a another layer of the printed circuit board. The signal channel is terminated with termination resistors as shown.
The system utilizing DRAMS may typically be capable of transferring data at rates up to 800 MHz using both edges of a 400 MHz clock. For optimal operation, the system must present a uniform bandpass impedance to high order harmonies of the fundamental clock frequency so as to minimize the change in current on each signal trace with respect to time. In order to meet this requirement stringent constraints are placed on the design of the signal channel. A channel design that conforms to these constraints in order to operate with the above described high speed DRAMs is referred to as a RAMBUS channel.
In a RAMBUS channel layout, the channel signal layer must be directly above a ground plane layer, separated only by a dielectric, with no intervening layers. Further, no vias are allowed to connect signal traces to another layer of the board. These vias are not allowed because they deteriorate the bandwidth of the channel.
The RAMBUS specification further requires that the impedance of the channel as seen by the controller is to be in the range of 25-50 Ohms with all components installed. The impedance of the channel is determined by the trace width, the dielectric thickness, the dielectric constant, and the spacing of the DRAMs. Increasing the trace width decreases the channel impedance. Increasing the dielectric thickness or increasing the spacing between DRAMs increases the channel impedance. Each signal trace may be viewed or modelled as a transmission line with a distributed series inductance and distributed parallel capacitance. The connection of a DRAM lead to the signal trace may be viewed as placing a capacitance in parallel with the transmission line. The signal trace parameters are chosen so that the parallel combination of the transmission line impedance and the DRAM impedance is in the range of 25-50 Ohms. Formulas for deriving the impedance of the channel as a function of the trace width, dielectric thickness, and DRAM spacing have been developed and are well known in the art.
Notice, as shown in
FIG. 1
, that in RAMBUS applications the signal leads of the DRAM are aligned on one side of the chip and the corresponding leads on multiple DRAMs are spaced apart by an amount that is greater than the width of the DRAM. The DRAMs are typically spaced as close together as practical, given the constraint of designing the lead lengths so that the channel exhibits an impedance in the range of 25-50 Ohm, in order to conserve board space.
It would be desirable to conserve board space even further by stacking the DRAMs one on top of another. High density stacked memory modules have been developed as disclosed in U.S. Pat. Nos. 5,279,029, 5,367,766, 5,455,740, 5,484,959 and 5,592,364, all of which are incorporated herein by reference for all purposes.
A half sectional view of a typical embodiment of a stacked package
11
is shown in FIG.
2
. The memory modules
16
are stacked vertically so that the leads
14
which extend from the sides of each module are aligned in vertical columns. The leads
14
in each vertical column may be sized and formed so as to securably mate with a vertical rail
12
. Each vertically oriented rail
12
may be formed of substantially planar material having perimeter edge and two planar, relatively wide, side surfaces. The leads of each vertical column mate with the edge of the rail
12
. The rails electrically couple the leads to connections on the printed circuit board as at
28
. The leads
14
also provide heat dissipation by conducting heat away from the stacked memory modules
16
. Variations of the basic configuration shown in
FIG. 2
are disclosed in the above-referenced U.S. patents.
The stacked memory module package increases the spatial density of system memory, thereby decreasing the area of printed circuit boards which must be reserved for memory. Therefore, a means for achieving a stacked memory configuration compatible with a RAMBUS channel layout is desirable to increase RAMBUS DRAM memory density and conserve space.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a stacked memory configuration that is compatible with the RAMBUS channel layout. In one embodiment of the present invention, two DRAM memory modules are stacked on top of each other. The lower module has electrical leads extending from one side of the package. The upper module has electrical leads which extend from the side of the package which is opposite to the side of the package from which the electrical leads of the lower module extend. The electrical leads are electrically and securably connected to vertically oriented rails located opposite each side of the stacked memory modules. Both the upper and lower modules may have mechanical leads extending from sides of the modules opposite the sides from which the electrical leads extend. The mechanical leads provide means for mounting individual modules, and are not electrically connected to the integrated memory circuit located within the module. In one embodiment, the external portion of the mechanical leads may be connected to the vertical rails to aid in heat dissipation. In an alternative embodiment, the mechanical leads may be physically removed.
The RAMBUS compatible configuration of the present invention is achieved by stacking one of the two modules in the stacked configuration in an upside-down position with respect to the other. This way, the corresponding electrical leads of each memory module will extend on opposite sides of the stacked package and will be securably connected to vertical rails. The vertical rails are electrically and securably connected to the bonding pads which electrically connect to the RAMBUS signal channel.
In this embodiment, the electrical leads of one memory module electrically connect to the signal channel at points located on one side of the stacked package and the electrical leads of the other memory module connect to the signal channel at points located on the opposite side of t
Cady James W.
Rapport Russell
Denko J. Scott
Elms Richard
George & Donaldson, L.L.P.
Nguyen Tuan T.
Staktek Group L.P.
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