Rambus dynamic random access memory

Details Rambus dynamic random access memory Rambus dynamic random access memory

2005-04-12

2005-04-12

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S005000, C365S189090

Reexamination Certificate

active

06880039

ABSTRACT:
Disclosed is a Rambus DRAM capable of reducing power consumption and layout area by enabling data read/write control signal of accessed memory bank only, in a top memory bank and a bottom memory bank. The disclosed comprises: a top and a bottom memory bank blocks including a plurality of unit memory banks, respectively; and a data read/write control signal generation block for generating a top data write control signal and a top data read control signal to the top memory bank block and a bottom data write control signal and a bottom data read control signal to the bottom memory bank block, thereby controlling the top memory bank block and the bottom memory bank block to separately operate in data read/write operations.

REFERENCES:
patent: 6138202 (2000-10-01), Nilsen
patent: 6362995 (2002-03-01), Moon et al.
patent: 6507886 (2003-01-01), Chen et al.
patent: 6535450 (2003-03-01), Ryan et al.
Derwent Acc. No. 2002-412263, Park N G, KR 2001109645 A, Dec. 2001, 3 pages.

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