Rambus DRAM with clock control circuitry that reduces power...

Details Rambus DRAM with clock control circuitry that reduces power... Rambus DRAM with clock control circuitry that reduces power...

2000-11-30

2004-02-03

Butler, Dennis M. (Department: 2185)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S322000, C713S600000

Reexamination Certificate

active

06687843

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a Rambus DRAM. More specifically, the invention relates to an improved Rambus DRAM which can reduce power consumption by restricting generation of an unnecessary clock by improving command decryption when a command is applied with a COLC packet or COLX packet, so that the other packet cannot influence on another device.
2. Description of the Background Art
In general, a Rambus DRAM is a packet driving memory device for transmitting packet type data and control signals. Typically, a plurality of Rambus DRAMs are connected on a Rambus channel. Each Rambus DRAM is controlled by a Rambus memory controller through the Rambus channel. Here, the controller and the Rambus DRAMs respectively include an interface in order to transmit/receive a data to/from each other through the Rambus channel.
The plurality of Rambus DRAMs connected on the Rambus channel are controlled by one controller, and thus have different phase differences so as to recognize the data and control signal in an identical time. That is, the Rambus DRAM far from the controller rapidly processes the data, and the Rambus DRAM near the controller slowly processes the data.
A command packet in the Rambus DRAM includes a primary control packet (PCP) and a secondary control packet (SCP). Referring to
FIGS. 1 and 2
, the SCP is divided into a COLC packet (
FIG. 1
) and a COLX packet (FIG.
2
).
As shown therein, the SCP is synchronized with a CTM/CFM clock, and thus a command is applied consecutively through five pins COL
0
, COL
1
, . . . , COL
4
.
In the COLC packet (FIG.
1
), DC[4:0] denotes a device address where the command will be performed, and COP[3:0] denotes a command OP_code (here, OP_code implies a command code applied from an external channel). In addition, BC[3:0] denotes a bank address, and C[5:0] denotes a column address.
In the COLX packet (FIG.
2
), DX[4:0] denotes a device address, and XOP[4:0] denotes a command OP_code. BX[3:0] denotes a bank address.
According to the COP[3:0] of the COLC packet, various commands including the read, write and precharge operations can be performed. According to the XOP[4:0] of the COLX packet, the current control and precharge operations can be carried out.
The COLC packet and the COLX packet can be combined and applied at the same time. In this case, the SCP can simultaneously apply a command to two devices.
When an S bit becomes ‘1’, the two packets receive a serial data for 4 cycles, and enter into a decoding process. When the command is applied to one device by using one of the two packets, the S bit must have a value of ‘1’, and thus the other packet also enters into the command decoding process. Since the command decoding process is performed on the unnecessary packet, a NO operation command is externally applied. However, a device ID in each packet is always matched with one of the 32 devices on a module (because device ID bits are 5 bits). In this case, another device enables an internal clock signal tclk by enabling an internal signal idhit_cas_ff1 (or idhit_cas_othr), which is called a glitch phenomenon. Whenever such a command is applied, power is unnecessarily consumed.
FIG. 3
(Prior Art) is a diagram of a conventional circuit for generating a clock enable signal tclk_en for generating the clock signal tclk. The conventional circuit includes an input signal detecting unit
10
for receiving a signal idhit_cas_ff1 detecting whether a value of DC[4:0] is identical to its device address and a signal idhit_cas_othr detecting whether a value of DX[4:0] is identical to its device address, and for enabling an output signal etck_en when at least one signal is enabled. An output signal maintaining unit
20
generates a control signal ten_in1_b for maintaining an enable state of the clock enable signal tclk_en outputted in the read or current control command. An output signal control unit
30
receives the output signal etck_en from the input signal detecting unit
10
, and generates a control signal ten_in2_b for disabling the output signal tclk_en when the command is not the read or current control command. A signal generating unit
40
receives the signal idhit_cas_ff1, the signal idhit_cas_othr, the output signal ten_in1_b from the input signal detecting unit
20
, and the output signal ten_in2_b from the output signal control unit
30
, and generates the clock enable signal tclk_en.
When the command is applied by using the SCP command packet on the Rambus DRAM module (maximally
32
devices), the respective Rambus DRAMs on the module compare DC[4:0] and DX[4:0] with their device addresses. Each Rambus DRAM converts the signal idhit_cas_ff1 to a high level when the value of DC[4:0] is identical to their device addresses, and converts the signal idhit_cas_othr to a high level when the value of DX[4:0] is identical to their device addresses.
In the conventional circuit for generating the clock enable signal tclk_en, when one of the signals idhit_cas_ff1, idhit_cas_othr is at a high level, the output signal tclk_en from a NAND gate NA
3
of the signal generating unit
40
becomes a high level, thereby generating the clock signal tclk. In addition, the output signal etck_en from a NAND gate NA
1
of the input signal detecting unit
10
also becomes a high level, and thus an enable terminal EN of a flip-flop FF
4
becomes a high level. Accordingly, the output signal ten_in2_b from the flip-flop FF
4
is at a low level. Therefore, if not set through a set terminal S(Q=1), the output signal tclk_en from the NAND gate NA
3
is maintained at a high level.
When the output signal ten_in1_b from the output signal maintaining unit
20
generated due to a special command (not the read or current control command) is at a high level, the output signal ten_in2_b from the flip-flop FF
4
of the output signal control unit
30
is set after three cycles (the signal etck_en is consecutively transmitted, and thus the signal etck_en_rst becomes ‘1’), thereby converting a high value of the clock enable signal tclk_en to a low level.
That is, when a sequence of applying a command to one of the 32 devices on the module with one of the COLC and COLX packets is consecutively carried out, toggling of the unnecessary clock signal tclk occurs in three cycles in the device identical to the device address value of the other packet (value of DC[4:0] of the COLC packet or DX[4:0] of the COLX packet).
For example, when the 32 Rambus DRAMs are on the module, if the read command (COP=0011) is externally applied to the 10
th
device (DC=01010) with the COLC packet, the value of the COLX packet is generally ‘DX=00000’ and ‘XOP=00000’. In this case, since the value of DX is ‘0’, the signal idhit_cas_othr informing that the device ID is matched in the 0
th
device becomes a high level. Accordingly, toggling of the clock signal tclk occurs in the 0
th
device as well as the 10
th
device. Thereafter, since the value of XOP is ‘0’, the clock signal tclk is disabled after three cycles.
FIG. 4
shows an operation timing of a COL packet of the conventional Rambus DRAM. When the signal idhit_cas_othr(h) becomes a high level by applying the command with the COLX packet, the clock enable signal tclk_en(d) becomes a high level, and thus a clock signal tclka(e) and a clock signal tclkb(f) are operated, thereby generating a pulse. However, when it is judged that the command is not the read or current control command, the clock enable signal tclk_en(d) is disabled after three cycles, thereby controlling generation of the clock signals tclka, tclkb(e)(f).
In the conventional Rambus DRAM, when the SCP command is applied, the internal clock enable signal tclk_en becomes a high level, and thus the clock signal tclk is enabled. Thereafter, according to the command analysis result, if the applied command is not the read or

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