Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2000-08-08
2001-10-30
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230030, C365S203000, C365S233100, C365S230080, C365S226000, C365S227000
Reexamination Certificate
active
06310814
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor memory, and more particularly to managing refresh and current control operations in a memory subsystem.
BACKGROUND OF THE INVENTION
The main operating memory of virtually all modern desktop and laptop computers is implemented using dynamic random access memory (DRAM) components. DRAM is relatively inexpensive and provides excellent storage density relative to other types of semiconductor memory.
A defining characteristic of DRAM is that the individual storage cells in a DRAM component usually cannot hold their charge for more than about 70 milliseconds. Consequently, to prevent loss of data, each cell in the DRAM component is periodically sensed (read) and rewritten in a refresh operation.
The fundamental aspects of DRAM refresh are the same for virtually every type of DRAM including Fast Page Mode (FPM) DRAM, Extended-DataOut (EDO) DRAM, Synchronous DRAM (SDRAM) and others. An activate operation is performed to enable the contents of a row of memory cells onto respective bitlines where they are sensed by an array of sense amplifiers. Because sensing the memory cells is destructive to the cells' contents, the outputs of the sense amplifer array are routed back to the respective bitlines to restore the appropriate charge levels to the memory cells. Thus, it is the activate operation that actually refreshes the contents of DRAM memory cells. After the activate operation is completed, a precharge operation is performed to close the sense amplifier array. In a precharge operation, memory cells in an activated row are decoupled from their respective bitlines and the sense amplifer array charges the bitlines to a voltage level that is approximately midway between the memory cell charge voltages for a “1” and a “0”. The memory cells and bitlines are now ready for subsequent activation. Because the sense amplifier array output is set to the precharge voltage to charge the bitlines, any data that had been captured in the sense amplifier array is lost in the precharge operation. For this reason, a precharge operation is said to “close” the bank associated with the sense amplifier array. After a sense amplifier array has been closed, it is ready for use in a subsequent activate operation.
Because refresh operations consume DRAM bandwidth that could otherwise be used for data read and write transactions, it is desirable to reduce the time spent performing refresh operations. Unfortunately, core logic constraints and the limited command interface of most DRAM devices limits the extent to which refresh overhead can be reduced without sacrificing device operability. For example, in conventional DRAM devices there is often only one sense amplifier array. Because there is only one sense amplifier array, only one row of memory cells can be refreshed at a time and the total time to refresh all the rows in the device is simply the number of rows times the refresh time per row.
In more modern devices, such as synchronous DRAM devices (SDRAM), two sense amplifier arrays are often included within a single component. The memory cells in the SDRAM are partitioned into banks with each bank being serviced by one of the two sense amplifier arrays. Using this arrangement it is possible to perform certain interleaved operations on the different banks. For reasons discussed below, however, it is usually not possible to perform interleaved refresh operations without sacrificing the ability to place the SDRAM in a reduced power state.
SDRAM devices typically provide two modes for refresh. In one mode, called CBR refresh (Column Address Strobe Before Row Address Strobe), a CBR refresh command is issued to the SDRAM device to refresh a row and bank indicated by refresh logic within the SDRAM. The SDRAM's internal refresh logic typically includes a row counter that is incremented after each CBR refresh command to indicate the next row to be refreshed. When the SDRAM device enters a reduced power state, logic within the SDRAM continues to refresh the row indicated by the internal counter and to increment the row counter. As a result, no loss of continuity in the sequence of refreshed rows occurs when the device is transitioned between normal and reduced power states. A significant drawback to CBR refresh operation, however, is that both banks must typically be closed before a CBR refresh operation is initiated. Consequently, the potential for performing concurrent refresh operations in the respective SDRAM banks is usually not realized in CBR refresh mode and the total time to refresh a device is still the number of rows times the refresh time per row.
Another mode of refreshing an SDRAM device is a controller-sequenced refresh mode. In the controller-sequenced refresh mode, the memory controller issues activate and deactivate (precharge) commands to each row in the SDRAM in a bank alternating sequence. Because an activate operation can be performed on a row in one bank while a deactivate is being performed on a row from another bank, the controller-sequenced refresh mode allows rows from respective banks to be concurrently refreshed, thus reducing the elapsed time required to refresh the entire SDRAM device.
A significant disadvantage of the controller-sequenced mode is that it is usually difficult to place an SDRAM, operated in the controller-sequenced refresh mode, into a reduced power state without loss of data. So long as the SDRAM remains in normal (e.g., fully powered) operating state, the memory controller supplies the address of each row being refreshed and the memory controller is therefore aware, at any given time, which row is to be refreshed next. However, when the SDRAM is transitioned to a reduced power state, the SDRAM's internal row counter is used to supply the address of the row being refreshed and the row counter is periodically incremented so long as the SDRAM remains in the reduced power state. As a result, when the SDRAM is returned to the normal operating state, the address of the next row to be refreshed is typically unknown to the memory controller and a burst of refresh operations must therefore be issued to refresh each row in the SDRAM in whatever remaining time may be left in the refresh interval, tREF (tREF is the time interval within which each row in a DRAM device must be refreshed). In many SDRAM devices, it is not possible to refresh all of the rows in the SDRAM in such a remaining portion of the refresh interval so that the controller-sequenced refresh mode cannot be used with reduced power operation without the danger of some row failing to be refreshed within the proper interval. Thus, a designer using SDRAMs must usually make a choice: either use the slower CBR refresh mode so that reduced power operation can occur, or use the controller-sequenced refresh mode and disallow reduced power operation to prevent an improper refresh operation when transitioning between power states.
In another multi-bank device called the Concurrent Rambus™ DRAM (Concurrent RDRAM®) developed by Rambus, Inc. of Mountain View, Calif., a command structure is provided that allows refresh commands directed to different banks to be interleaved. However, the underlying Concurrent RDRAM core logic does not permit concurrent activate and precharge operations to be performed on different banks. Consequently, though the refresh commands may be interleaved, concurrent refresh operations are not performed.
SUMMARY OF THE INVENTION
A method and apparatus for performing concurrent refresh operations in a memory device having a dynamic memory array with at least two banks, each bank including a plurality of rows of memory cells. The memory device receives an activate request identifying a bank in which a row is to be activated. The row to be activated is specified by a row register in the memory device. The memory device performs the activate operation on the row in the identified bank in response to the activate request. The memory device receives a precharge request that specifies the bank identified in the activa
Barth Richard M.
Davis Paul G.
Hampel Craig E.
May Bradley A.
Satagopan Ramprasad
Pennie & Edmonds LLP
Rambus Inc.
Tran Andrew Q.
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