RAM store and control method therefor

Details RAM store and control method therefor RAM store and control method therefor

2006-09-19

2006-09-19

Auduong, Gewne N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S203000

Reexamination Certificate

active

07110310

ABSTRACT:
The invention relates to a RAM store having a shared SA structure, in which sense amplifiers (SA) arranged in SA strips (10) between two respective adjacent cell blocks are used by a plurality of bit line pairs (21, 22; 21–24) from the adjacent cell blocks and the bit line pairs (21, 22; 21–24) have respective charge equalization circuits individually associated with them for the purpose of performing charge equalization between the bit line halves of the bit line pairs (21, 22; 21–24) in a precharge phase, where a shorting transistor (30) is provided which, when prompted by a control signal (EQLx), connects the bit line halves (BLT, BLC) of the bit line pairs (21, 22; 21–24) which are in the precharge phase to one another. The shorting transistor (30) is arranged in or on the respective sense amplifier (SA) jointly for all bit line pairs (21, 22; 21–24) which can be connected to a repetitive sense amplifier (SA), and it can be switched by a separate shorting control signal (EQLx) via a dedicated control line (9).

REFERENCES:
patent: 5894444 (1999-04-01), Seyyedy
patent: 6301175 (2001-10-01), Seyyedy et al.
patent: 6504777 (2003-01-01), Hsu et al.
patent: 2001/0015928 (2001-08-01), Fujioka et al.
patent: 2002/0051393 (2002-05-01), Taito et al.

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