RAM macro and timing generating circuit thereof

Details RAM macro and timing generating circuit thereof RAM macro and timing generating circuit thereof

2011-08-16

2011-08-16

Sofocleous, Alexander (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S201000, C365S233100

Reexamination Certificate

active

08000157

ABSTRACT:
A timing generating circuit generates a control clock (1) and a test clock (2) based on an externally input clock CLK, and outputs the generated clocks to a testing circuit. The control clock (1) is a signal the phase of which is delayed by a predetermined amount with reference to the clock CLK. This predetermined amount can be set/changed with an external test signal. The test clock (2) is nearly an inversion signal of the clock CLK. The testing circuit generates various types of control signals (4) based on either of the clocks (1) and (2), and distributes the signals to a controlling circuit. Which of the clocks (1) and (2) is selected in the testing circuit can be set with an external test signal.

REFERENCES:
patent: 4608669 (1986-08-01), Klara et al.
patent: 4916670 (1990-04-01), Suzuki et al.
patent: 5226011 (1993-07-01), Yanagisawa
patent: 5576996 (1996-11-01), Awaya et al.
patent: 5764592 (1998-06-01), McClure
patent: 5910181 (1999-06-01), Hatakenaka et al.
patent: 5973990 (1999-10-01), Sakurai
patent: 6643807 (2003-11-01), Heaslip et al.
patent: 6757212 (2004-06-01), Hamamoto et al.
patent: 6829728 (2004-12-01), Cheng et al.
patent: 2001/0033519 (2001-10-01), Koshikawa
patent: 2004/0260975 (2004-12-01), Nagura
patent: 2005/0117422 (2005-06-01), Urayama et al.
patent: 01-196790 (1989-08-01), None
patent: 02-089300 (1990-03-01), None
patent: 03-230395 (1991-10-01), None
patent: 04-134695 (1992-05-01), None
patent: 07-29375 (1995-01-01), None
patent: 08-083498 (1996-03-01), None
patent: 10-233099 (1998-09-01), None
patent: 11-144497 (1999-05-01), None
patent: 2001-243800 (2001-09-01), None
patent: 2001-307499 (2001-11-01), None
patent: 2002-42466 (2002-02-01), None
patent: 2004-22014 (2004-01-01), None
patent: 2004-158144 (2004-06-01), None
patent: 2005-141817 (2005-06-01), None
patent: 2005-235364 (2005-09-01), None
European Search Report mailed May 13, 2009 and issued in corresponding European Patent Application 06714793.4.
International Search Report issued Oct. 24, 2006 in corresponding PCT/JP2006/303656.
Japanese Office Action issued on Mar. 29, 2011 in related Japanese Patent Application No. 2008-502566.

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