RAM configurable redundancy

Details RAM configurable redundancy RAM configurable redundancy

1998-12-23

2001-03-06

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

06198675

ABSTRACT:

TECHNICAL FIELD
This invention relates to replacing a defective memory line with a usable memory line, and in particular, to the use of an available memory line within the same memory array block as the defective line.
BACKGROUND OF THE INVENTION
It is known that in a large memory array, some memory cells may be defective. It is, of course, possible to discard an entire memory array if one or more cells in the array are defective. On the other hand, it is known in the art that if the number of memory cells which are defective in a given array are few in number, it may be possible to replace these memory cells with usable memory cells on the chip which are not defective.
FIG. 1
shows a memory array having redundant memory cells according to one configuration as used in the prior art. According to this configuration, the array contains main memory blocks, in this instance labeled blocks
1
-
4
. Associated with the main memory block is a row address circuitry and a column address circuitry which can also support defective rows and columns.
One of the blocks may contain a row having two or more defective memory cells, thus causing the entire row to be defective. Further, the memory array may include two or more defective memory cells in a column, causing the entire column to be indicated as defective. According to one prior art technique, the address of the respective defective row or defective column is programmed into the address circuitry of the memory array to prevent access the defective row or column. This programming can take place by blowing fuses in the address circuitry for the defective memory line, thus prohibiting the line being addressed by either the row address circuitry or the column address circuitry.
In one prior art technique, it may be desired to replace the defective memory line with an extra line positioned in a different location on the chip, usually called a redundant line. In such an instance, the address of the redundant line may be stored in the respective row and column address circuitry as a substitute for the defective line. When an attempt is made to address a defective line, the address for a redundant line is substituted by the address circuitry so that data is stored in or retrieved from the redundant line rather than the defective line.
The prior art technique provides the advantage that the entire memory chip does not need to be discarded if there are only a few defective lines in the chip. However, a significant disadvantage is that longer access time is required to access the redundant line than is required for accessing a line in the main memory. This is because of the time required to determine that an attempt has been made to address a defective line and to substitute therefor the address of the redundant line and then to address this redundant line.
There are a number of schemes for providing redundant memory cells to replace defective memory cells in a large array. See, for example, any one of the following U.S. Pat. Nos. 5,574,688; 5,572,470; 5,566,114; 5,659,509; 5,602,786; and 5,559,743. These above patents describe various schemes for replacing defective memory cells with redundant memory cells and then providing addressing to the redundant memory cells.
SUMMARY OF THE INVENTION
According to principles of the present invention, a memory array is configured to provide fast access to a redundant line in a memory array to replace a defective line. The identification of a defective line is stored in a software program associated with the memory. The term line as used herein refers to either a row line or a column line. When the memory is prepared for use, the program is loaded into an access register. The access register contains identification of a defective line in the memory associated with that particular register. When an attempt is made to address a defective line in the memory, the access register automatically directs the address signal to an alternative line which is not defective. The data can then be stored in or read from the redundant line and use of the defective line is avoided.
According to one embodiment, the alternative redundant line is the next adjacent line in the array block. This has the advantage that extremely fast access time to the redundant line can be provided. Since the address has been completely decoded, all that is necessary is to step the line access signal from the present line to the next adjacent line and then access the memory. Such stepping of the access signal is a very high-speed operation and thus access time to and from the memory is not significantly altered by the presence of a defective line.
According to one embodiment, the register associated with each respective line is a 1-bit register. Each register is associated with a particular block within the memory array. Each of the registers is stored with a selected bit pattern based on the location of the defective line in the array. In particular, the bit pattern begins as a sequence of bits having the same value. At the location of the defective line, the value of the bits transitions to a different binary value, the point of transition marking the location of the defective line within that particular block of the array. Therefore, at the transition point the line associated with the transition point is not addressed and instead the next adjacent row is addressed. As each subsequent adjacent row in the memory is addressed, each of the memory lines being accessed is shifted down 1 from the actual addresses presented.
According to one embodiment, the shifting is provided by having the output of the register control a select line on a multiplexer, the multiplexer having two inputs and one output. In the event the line is prior to a defective line, then a first input of the multiplexer is selected as the output. On the other hand, if the address is at or after a defective line then the register causes the selection of a second input for the output of the particular multiplexer, thus shifting the actual line to be addressed down 1. The present invention thus provides the advantage of extremely fast access time to the memory, even when a redundant line is being accessed.


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