Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-06-27
2003-11-04
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230060, C365S210130, C365S189080
Reexamination Certificate
active
06643198
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a RAM (Random Access Memory) circuit having a memory cell array in the form of a matrix-type configuration of rows and columns. The total number of the rows includes a number of regular rows and a number of redundant rows and each row is assigned a word line for activating and deactivating the memory cells of the relevant row.
In RAMs of the aforementioned type, each word line is connected to a dedicated driver containing a plurality of switching elements, usually field-effect transistors (FETs), which respond to control signals in order to put the relevant word line either at an activation potential or at a deactivation potential. Only in the activated state of a word line are the memory cells of the associated row conditioned for a write or read access, the access itself being effected via bit lines assigned to the individual columns of the cell array.
In the layout of an integrated circuit, the aforementioned word line drivers are arranged in a driver array along one of the column-parallel edges of the cell array where the input-side ends of the word lines are situated. In large scale integrated memory chips, the pitch of the word lines (e.g. 0.17 &mgr;m center-to-center distance) is significantly smaller than the width—running in the column direction—of each individual transistor of the drivers. Consequently, each driver extends of necessity over the width of a plurality of word lines in the column direction. This makes it necessary to arrange in each case a plurality of drivers offset (that is to say spatially “one behind the other”) in the row direction, the number p of the drivers in each of these groups being at least as large as the number of word lines which find space within the required width of a driver. Each driver group is thus assigned to a group of p adjacent word lines.
For reasons of memory organization and with the aim of economic utilization of the chip area, it is advisable and customary to choose the number p of drivers or word lines per group (that is to say the “group strength”) such that the total number n of regular rows or word lines is divisible by p without remainder and, consequently, an integer number g=n/p of groups is fully occupied. In this case, each word line is uniquely selectable through the use of an input address which is applied to the memory chip and is hierarchically composed of exactly one of g possible group addresses which identifies the relevant word line group, and exactly one of p possible position addresses which identifies the position of the word line within the respective group. Accordingly, a word line decoder is constructed hierarchically in two stages: a 1-out-of-g group decoder which responds to the group address addresses the respective driver group, and each of the g driver groups is configured, for its part, as a 1-out-of-p decoder which responds to the position address in order to drive the addressed word line within the relevant group.
For layout reasons the drivers must be spatially arranged such that they occupy locations in a regular pattern. Each location is determined by an X coordinate measured in the row direction and a Y coordinate measured in the column direction. Given a number of rows n+r and a group strength p, there are p possible X coordinates and (n+r)/p possible Y coordinates, if n+r is an integer multiple of p, with n being the number of regular rows and r being the number of redundant rows.
The redundant rows and word lines serve for repairing the cell array, i.e. for replacing defective rows, if the test run of the memory has demonstrated such defects. This replacement is done, in principle, by reprogramming the addresses of the word lines of defective rows through the use of generally known fuse technology within the decoding device into addresses of redundant word lines, so that the input addresses themselves can be maintained unaltered.
The reprogramming of the addresses is simpler, the fewer bits of an input address have to be reprogrammed. The fuse technology used for this purpose becomes the least complicated if, in the case of a defective row, all p rows of the relevant group of rows are replaced by a whole group of p redundant rows, because then only bits of the group address need to be changed. For this reason, the number r of redundant word lines is usually likewise an integer multiple of the group strength p, so that the same hierarchical address structure (group addresses with in each case p position addresses) as for the regular word lines holds true. Although a groupwise repair entails the risk of a certain degree of waste, this can be kept within limits if it is taken into consideration that defects often occur in clusters anyway, that is to say simultaneously encompass a plurality of adjacent word lines. Nevertheless, the practice of groupwise repair requires that, for a given number of regular rows, more redundant rows have to be provided than in cases where it is possible to repair individual rows or bundles of rows which are smaller than the group strength p.
Important criteria for the number of redundant rows to be chosen are the associated increase in area and the exploitation or defect probability of the regular rows. An excessively small number of redundancies leads to memories that cannot be completely repaired, while too many redundant rows increase the chip area unnecessarily. In the case of large memories (e.g. above 256 MB), it is allowable, under certain circumstances, to replace an entire group of e.g. p=4 regular rows by an equally sized group of redundant rows (so-called quadruple redundancy) even if only one row in the group is defective. In the case of smaller memories, however, it is advisable to subdivide the repair possibilities more finely. Thus, in the case of a 128 MB-DRAM, for example, it is recommendable to provide, for 1024 regular rows in each case, 12 redundant rows and the possibility of pairwise repair, so that the repair supply includes 6 pairs.
In earlier times, the redundant rows were positioned in a common contiguous block at an outer edge of the cell array. Advantages may be afforded, however, by departing from this practice and arranging the quantity of redundant rows as two separate subsets in two different sections of the cell array.
One of these advantages is ensuring a “topologically correct” repair if a so-called bit line twist is present in the cell array. This is understood as the known measure of transposing selected bit line cores at a location within the cell array, the so-called “twist region”, in order to reduce the risk of undesirable signal coupling. The twist has the effect that the sections of the cell array have a different data topology on both sides of the twist region, i.e. the pattern of the assignment between the polarity of the memory cell charge and the data evaluation on the bit lines is different on one side of the twist region than on the other side. Only if redundant rows are present on each side can a defective row always be replaced by a redundant row of the same data topology.
Furthermore, it may be expedient, even with no twist present, to position redundant rows at both edges of the cell array. This reduces the defect probability for regular rows, because the defect risk is greater at the edges than in the interior of the cell array.
Dividing the redundant rows between two sections of the cell array poses no problems if the number of such rows in each of the two sections is an integer multiple of the group strength p. However, this requires the total number r of redundant rows to be an integer multiple of p. This means, however, e.g. given the group strength p=4, that the possible total number of redundant word lines is limited to 16 or 24 or 32, etc. A problem arises if one wishes to choose a different number (e.g. 12) for the reasons presented further above. This is because the situation then arises wherein the number of rows is not an integer multiple of p in each of the two sections, unless the to
Fischer Helmut
Zimmermann Ellen
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Nelms David
Stemer Werner H.
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