RAM cells having a substantially balanced number of N-MOS...

Details RAM cells having a substantially balanced number of N-MOS... RAM cells having a substantially balanced number of N-MOS...

1999-09-16

2001-07-17

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S154000

Reexamination Certificate

active

06262932

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to Complementary Metal-Oxide-Semiconductor Random Access Memories (CMOS RAMs), and more particularly to using a balanced number of N-MOS and P-MOS transistors in a RAM cell to save layout area.
2. Description of the Background Art
CMOS RAM cells comprise N-MOS and P-MOS type transistors, each type of which requires layout areas separate from the other type.
FIG. 1
shows a prior art two-port RAM cell
100
that includes two P-MOS transistors P
126
and P
134
and eight N-MOS transistors N
106
, N
130
, N
138
, N
108
, N
110
, N
114
, N
118
, and N
122
. Transistors P
126
and N
130
form an inverter I
102
while transistors P
134
and N
138
form an inverter I
104
. The two inverters I
102
and I
104
are “cross-coupled,” that is, the output of inverter I
102
is connected to the input of inverter I
104
and the output of inverter I
104
is connected to the input of inverter I
102
.
Lines BL
1
, BL
2
, BL
1
N, and BL
2
N are referred to as “bit lines.”
Line WL
1
, together with transistors N
106
, N
130
, N
138
, and N
108
, is referred to as a read-write port since line WL
1
enables both reading from and writing to RAM cell
100
. Line WL
2
, together with transistors N
110
, N
114
, N
118
, and N
122
, is referred to as a read-port because line WL
2
enables only reading from RAM cell
100
. Lines WL
1
and WL
2
are also referred to as “word lines.”
RAM cell
100
has significantly fewer P-MOS transistors than N-MOS transistors, i.e., two P-MOS transistors P
126
and P
134
versus eight N-MOS transistors N
106
, N
130
, N
138
, N
108
, N
110
, N
114
, N
118
, and N
122
. As the number of ports in RAM cell
100
increases, the unbalance between the number of P-MOS and N-MOS transistors increases.
FIG. 2
shows a prior art three-port RAM cell
200
, which is equivalent to RAM cell
100
with a second read-port WL
3
constituted by the four N-MOS transistors N
142
, N
146
, N
150
, and N
154
. RAM cell
200
thus has two P-MOS transistors P
126
and P
134
and 12 N-MOS transistors N
106
, N
130
, N
138
, N
108
, N
110
, N
114
, N
118
, N
122
, N
142
, N
146
, N
150
, and N
154
. The ratio of P-MOS transistors to N-MOS transistors of ¼ in cell
100
decreases to ⅙ in cell
200
. Because the ports are constituted by N-MOS transistors, this ratio continues to decrease as the number of ports increases. Consequently, since the layout areas for a P-MOS transistor and for an N-MOS transistor must be separated by at least the minimum distance specified by the layout design rules, the unbalanced number of P-MOS and N-MOS transistors wastes layout area.
FIGS. 3A and 3B
show two prior art layouts
300
A and
300
B for either RAM cell
100
or
200
. Layouts
300
A and
300
B each include areas P
304
for P-MOS transistors, areas N
308
for N-MOS transistors, and unused areas U
312
. The suffixes A and B correspond to layouts
300
A and
300
B, respectively. Unused areas U
312
are wasted and should be minimized. Even though layout
300
B is preferable to layout
300
A because the unused area U
312
B is smaller than the unused area U
312
A, both unused areas U
312
A and U
312
B increase the total layout area. Possibilities for reducing unused areas U
312
while providing the same RAM cell circuit are limited because layout design rules require a minimum spacing between area P
304
and area N
308
to separate P-MOS transistors from N-MOS transistors. The typical spacing requirement is 2.4 &mgr;m for 0.35 &mgr;m technology where 0.35 &mgr;m denotes the minimum manufacturable transistor gate length of the technology.
What is needed, therefore, is a method for improving the deficient layout schemes of the prior art, while maintaining circuit functionalities.
SUMMARY OF THE INVENTION
The present invention provides RAM cells having a substantially balanced number of N-MOS and P-MOS transistors to utilize layout resources. A port in the preferred embodiment is referred to as an N-port if it comprises four N-MOS transistors, and is referred to as a P-port if it comprises four P-MOS transistors. Further, read-write ports are of the same type, i.e., either an N-type or a P-type, while read-ports may be mixed. In a two-port RAM cell having one read-write port, the invention uses an N-read-write port and a P read-port. To form a three-port RAM cell comprising a read-write port and two read-ports, the invention uses an N read-write port, a P read-port, and an N read-port. In effect, the invention adds a second N read-port to the above-described two-port RAM cell to form the three-port RAM cell. To form a RAM cell having additional read-ports, the invention alternately adds a P-port and then an N-port to the RAM cell.
In a RAM cell having multiple N-read-write ports and multiple read-ports, the invention selects the number of P read-ports and the number of N read-ports such that the number of N-MOS transistors in the cell is as close as the number of P-MOS transistors as practical. For example, in a five-port RAM cell having three N read-write ports and two read-ports, the invention uses two P read-ports, which results in eight N-MOS transistors and eight P-MOS transistors. Similarly, in a six-port RAM cell having three N-read-write ports and three read-ports the invention uses P-ports for all three read-ports, which results in eight N-MOS transistors and ten P-MOS transistors. Using one N read-port and two P read-ports would result in twelve N-MOS transistors and eight P-MOS transistors.
In accordance with the invention, using an N-port to read data from the RAM cell pre-charges the corresponding bit lines to a high logic level. Conversely, using a P-port to read data from the RAM cell pre-charges the corresponding bit lines to a low logic level.


REFERENCES:
patent: 4910712 (1990-03-01), Camarota et al.
patent: 4975877 (1990-12-01), Bell
patent: 5477489 (1995-12-01), Wiedmann
patent: 5959931 (1999-09-01), Ueda
patent: 6026012 (2000-02-01), Hsue

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