RAM address decoding system and method to support misaligned mem

Details RAM address decoding system and method to support misaligned mem RAM address decoding system and method to support misaligned mem

1998-06-17

2000-06-13

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711109, 711127, 711129, 36523003, 36523004, G06F 1200

Patent

active

060761369

ABSTRACT:
A memory access system is provided for accessing a first data unit and a second data unit in a single memory access cycle. The memory access system provides at least a memory, an even address decoding circuit, an odd address decoder, and shift logic. The memory is interleaved by at least one address bus signal into an even memory bank and an odd memory bank. The even memory bank and the odd memory bank are each organized by a plurality of corresponding rows. Each one of the rows contains at least one storage location for a data unit, with one address mapped to one storage location. The even address decoding circuit decodes an address bus signal supplied to the input terminal and activates an output terminal coupled to enable the given row of the even memory bank. The odd address decoder decodes the address bus signal to activate an output terminal coupled to enable the row of the odd memory bank in which the first data unit resides. The shift logic processes input signals indicating a mis-aligned access of multiple data units to produce a shift signal, and the even address decoding circuit is responsive to the shift signal to increment or shift the output terminal activated by decoding the address bus signal. The first data unit is made accessible by enabling the given row of the odd memory bank, and the second data unit is made accessible by enabling the next sequential row of the even memory bank.

REFERENCES:
patent: 4381541 (1983-04-01), Baumann, Jr. et al.
patent: 4688188 (1987-08-01), Washington
patent: 4783736 (1988-11-01), Ziegler et al.
patent: 5353243 (1994-10-01), Read et al.
patent: 5625580 (1997-04-01), Read et al.
patent: 5848258 (1998-12-01), Fenwick et al.
patent: 5881009 (1999-03-01), Tomita

Affiliated with

Also associated with

Rating

RAM address decoding system and method to support misaligned mem does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with RAM address decoding system and method to support misaligned mem, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and RAM address decoding system and method to support misaligned mem will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2078918