Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-13
2003-02-25
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S377000, C257S382000, C257S384000, C257S386000
Reexamination Certificate
active
06525378
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to semiconductor-on-insulator devices and methods for forming the same. The invention relates particularly to semiconductor-on-insulator devices and methods for forming which avoid or reduce floating body effects and reduce contact resistance.
BACKGROUND ART
Silicon on insulator (SOI) materials offer potential advantages over bulk materials for the fabrication of high performance integrated circuits. Dielectric isolation and reduction of parasitic capacitance improve circuit performance, and eliminate latch-up in CMOS circuits. In addition, circuit layout in SOI can be greatly simplified and packing density greatly increased if the devices are made without body contacts (i.e., if the body regions of these devices are “floating”). However, partially-depleted metal oxide semiconductor field effect transistors (MOSFETs) on SOI materials typically exhibit parasitic effects due to the presence of the floating body (“floating body effects”). These floating body effects may result in undesirable performance in SOI devices.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is a semiconductor device. The device includes an SOI wafer including a semiconductor layer, a substrate and a buried insulator layer therebetween; the semiconductor layer including a source region, a drain region, and a body region disposed between the source and drain regions, at least one of the source and drain regions including an epitaxially raised region; and, a gate on the semiconductor layer, the gate being operatively arranged with the source, drain, and body regions to form a transistor; wherein the at least one of the source and drain regions including the epitaxially raised region includes a silicide region spaced apart from the body region by about 200 to about 1000 Angstroms (Å).
According to another aspect of the invention, the invention is a method of forming a semiconductor device. The method includes the steps of forming an SOI wafer having a semiconductor layer, a substrate and a buried insulator layer therebetween, wherein the semiconductor layer includes a source region, a drain region, and a body region disposed between the source and drain regions, at least one of the source and drain regions including an epitaxially raised region; forming a gate on the semiconductor layer before, during, or after the forming of the source, drain, and body regions; and, forming a silicide region in the epitaxially raised source or drain region such that the silicide region is spaced apart from the body region by about 200 to about 1000 Angstroms (Å).
REFERENCES:
patent: 5352631 (1994-10-01), Sitaram et al.
patent: 5659194 (1997-08-01), Iwamatsu et al.
patent: 6051473 (2000-04-01), Ishida et al.
Advanced Micro Devices , Inc.
Renner , Otto, Boisselle & Sklar, LLP
Thomas Tom
Tran Thien F
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