Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2001-11-28
2004-11-23
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
Reexamination Certificate
active
06822342
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor device fabrication. Specifically, the present invention provides a residue-free overlay target which enables precise alignment of lithographic masks or reticles while substantially preventing residue build-up at the surface of the semiconductor substrate and eliminating process steps associated with known overlay targets.
2. State of the Art
As is well known, state of the art semiconductor memory and processing devices include multiple layers of electronic features which must be fabricated using multiple process steps. Individual features of state of the art semiconductor devices are generally defined by photolithographic processes wherein a resist is applied over the surface of a semiconductor substrate, or a material layer overlying a semiconductor substrate, and individual device features are patterned into the resist using a mask or reticle. After patterning the resist, the device features are permanently defined in the material layer being processed or the underlying semiconductor substrate by wet or dry etch steps. Advanced processes used to fabricate state of the art semiconductor devices may require as many as fifteen or more separate patterning and etching steps at varying layers during the fabrication process. However, in order to consistently fabricate functional and reliable semiconductor devices, it is necessary that each pattern be accurately aligned over the semiconductor substrate or material layer being processed and the feature dimensions must be precisely defined at each patterning and etch step. This is particularly true for state of the art semiconductor devices which require tolerances in the tens of nanometers range.
To help ensure that the device patterns are accurately positioned, a mask or reticle may be aligned using overlay targets located outside the chip pattern defined on the wafer being processed. Overlay targets are generally etched into the semiconductor substrate or into an overlying material layer and, therefore, become a permanent part of the wafer being processed. As new layers are deposited, patterned, and etched, the new masks or reticles used to process the new layers are often aligned by referencing back to the permanent overlay targets previously defined in an underlying material layer.
Manual or automated registration tools may be used for pattern alignment which is generally accomplished by aligning overlay targets with marks included on the mask or reticle used. In state of the art fabrication facilities, however, automated registration tools are preferred because of their accuracy and high throughput capabilities. To accomplish their taks, such automated registration tools must be able to readily detect the edges of the pattern formed by the overlay targets. Yet, as will be described hereinafter, known overlay targets enable intermittent accumulation of process residue which obscures the edges of the overlay target patterns, thereby substantially interfering with the proper function of registration tools.
Known overlay targets generally include a pattern formed by one or more etched trenches or pad areas. Illustrated in drawing
FIG. 1
is a portion of an intermediate wafer structure
5
including a simple trench-type overlay target
10
. The overlay target
10
includes a continuous rectangular trench
11
etched into the semiconductor substrate
14
outside the chip pattern
15
. Of course, the overlay target depicted in drawing
FIG. 1
is provided for illustrative purposes only. It is understood that overlay targets can be created using a variety of patterns formed from continuous trenches, discontinuous trenches, or pad areas.
Depicted in drawing
FIG. 2
is a cross-section taken at line A—A of drawing
FIG. 1
, illustrating an overlying material layer
16
deposited over the surface
18
of the semiconductor substrate
14
after formation of the trench
11
defining the overlay target. As can be seen in drawing
FIG. 2
, the overlying material layer
16
tends to conform to the topography created by the trench
11
. Such conformation results in the formation of depressions
20
at the upper surface
22
of the overlying material layer
16
. Even after a polishing step, portions
24
(shown in drawing
FIG. 3
) of the depressions
20
may still remain and serve as collection points for process residue
26
(also shown in FIG.
3
), such as hemispherical grain (“HSG”) Poly. As is shown in drawing
FIG. 4
, because the residue
26
overlies the trench
11
defining overlay target
10
, the residue
26
works to obscure the outlines (depicted by dashed lines
28
a
and
28
b
) of the pattern formed by the trench
11
, making the outlines
28
a
and
28
b
of the overlay target
10
to appear ragged or inconsistent. Though drawings FIG.
2
through
FIG. 4
depict features associated with a trench-type overlay target, intermittent collection of obscuring residue is also an issue of pad-type overlay targets and overlay targets including one or more trenches or pads.
Though the build-up of process residue over an overlay target may occur only intermittently across the surface of a wafer, even one obscured overlay target may render mask or reticle alignment impossible or, at best, imprecise. For this reason, the surface of an incomplete wafer must be periodically cleaned, such as by patterning and etching steps, in order to ensure each of the overlay targets formed in the wafer are clean and easily registered by a registration tool. As is easily appreciated, such cleaning steps add time and cost to the fabrication process. Therefore, an overlay target which does not lead to the collection of obscuring process residue would be an improvement in the art, obviating the cost and delay associated with the cleaning steps currently undertaken to ensure the proper registration of overlay targets.
SUMMARY OF THE INVENTION
The present invention includes a residue-free overlay target, as well as a method of forming a residue-free overlay target, which answer the foregoing needs. The trenches or pads forming the residue-free overlay target of the present invention are broken down into a series of smaller raised lines which substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers. The residue-free overlay target of the present invention, therefore, prevents the formation of surface features which could serve as collection points for obscuring process residue, thereby eliminating the need to perform the intermediate cleaning steps otherwise necessary to ensure registration of overlay targets.
The method of forming a residue-free overlay target of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art. The method of the present invention includes providing a semiconductor substrate having top and bottom surfaces, depositing a resist layer, exposing the resist layer using a mask or reticle creating a resist pattern corresponding to at least one overlay target according to the present invention, developing the resist pattern, and executing a wet or dry etch to create at least one overlay target including a trench or pad area including a series of raised lines. As will be understood by those of skill in the art, the method of the present invention may be used to create overlay targets having a variety of patterns suitable for different semiconductor device fabrication processes, as well as different manual or automated registration tools. Moreover, the method of the present invention is easily modified for the fabrication of overlay targets in a variety of substrates.
Other features and advantages of the present invention will become apparent to those of skill in the art through a consideration of the ensuing description, the accompanying drawings, and the appended claims.
REFERENCES:
patent: 5128283 (1992-07-01), Tanaka
patent: 5677091 (1997-10-01), Barr et al.
patent: 5701013 (1997-12-01), Hsia et al.
patent
Baluswamy Pary
Bossart Tim H.
DeBoer Scott J.
Roberts Ceredig
Micro)n Technology, Inc.
TraskBritt
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