Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2005-02-17
2009-06-02
Patel, Hetul (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S112000, C711S154000
Reexamination Certificate
active
07543110
ABSTRACT:
A RAID disk array controller implements a write mask to support partial-stripe updates from a host system without expensive RAM to RAM copying and repeated disk accesses to assemble the updated stripe. New data from the host is transferred into a single buffer and a local processor tracks—by setting bits in the write mask—which segments of the target stripe are updated. The disk array is accessed to transfer the target stripe into the same buffer, but the buffer memory write enable is inhibited—responsive to the write mask—during transfer of the segments that were updated by the host. The complete, updated stripe is thus formed in a single buffer for parity calculations and write to the disk array.
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NVIDIA Corporation
Patel Hetul
Zilka-Kotab, PC
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