Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-12-06
1998-11-10
Decady, Albert
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711114, G06F 1100
Patent
active
058356940
ABSTRACT:
A data processing system incorporating the invention hereof, includes a host processor or server, connected to an array of disk drives which are further interconnected via a network. Each disk drive is logically divided into plural logical memory segments and, in the preferred embodiment, corresponding logical memory segments in each disk drive are arranged as a parity set in a RAID fashion. The host processor includes a driver which generates read and write commands to the array of disk drives. The commands include addresses which are in accord with ranges of addresses assigned to logical memory segments in each disk drive. Each disk drive stores an array configuration page which includes data that identifies a logical memory segment size; a first identifier for the disk drive that incorporates the respective memory segment; and a second identifier for the last disk drive which stores parity for the parity set including the logical memory segment. Each disk drive includes a controller for determining from the logical memory segment size and the second identifier, which logical memory segment in the respective memory stores parity data. The controller responds to an address accompanying a read or write command by mapping the address to a logical memory segment, other than the logical memory segment in the respective memory which stores parity data. Further, the controller, upon performing a write action to a logical memory segment, communicates directly with the disk drive that stores parity for the parity set of which the logical memory segment is a part and causes an update of that parity segment in accordance with the write action.
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De'cady Albert
International Business Machines - Corporation
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