Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-12-12
2006-12-12
Bragdon, Reginald G. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C714S006130
Reexamination Certificate
active
07149847
ABSTRACT:
A system and method for providing multiple disk fault tolerance in an N-column by R-row logical representation of stored elements in an array of N independent disks, R minus 1 being less than N divided by a number of disk failures F, includes assigning each strip containing data to at least F different parity groups so that each strip containing data in a respective column is assigned to parity groups different than other strips containing data in the column. The method also includes calculating, for each parity group, a parity value corresponding to all of the strips assigned to the parity group. The method further includes storing each of the parity values in strips of different columns, so that none of the strips containing data in a column are assigned to a parity group for which the parity value for the parity group is stored in the column.
REFERENCES:
patent: 5499253 (1996-03-01), Lary
patent: 5790774 (1998-08-01), Sarkozy
patent: 5805788 (1998-09-01), Johnson
patent: 5862158 (1999-01-01), Baylor et al.
patent: 6000010 (1999-12-01), Legg
patent: 6101615 (2000-08-01), Lyons
patent: 6138125 (2000-10-01), DeMoss
patent: 6148430 (2000-11-01), Weng
patent: 6158017 (2000-12-01), Han et al.
patent: 6327672 (2001-12-01), Wilner
patent: 6353895 (2002-03-01), Stephenson
patent: 6453428 (2002-09-01), Stephenson
patent: 6484269 (2002-11-01), Kopylovitz
patent: 6807605 (2004-10-01), Umberger et al.
patent: 6851082 (2005-02-01), Corbett
patent: 2002/0095616 (2002-07-01), Busser
patent: 2003/0084397 (2003-05-01), Peleg
patent: 2003/0163757 (2003-08-01), Kang et al.
patent: 2003/0167439 (2003-09-01), Talagala et al.
patent: 2003/0233611 (2003-12-01), Humlicek et al.
patent: 2004/0250161 (2004-12-01), Patterson
Chih-Shing Tau and Tzone-I Wang, Efficient Parity Placement Schemes for Tolerating Triple Disk Failures in RAID Architectures, 2003, IEEE, p. 1-2 [retrieved on May 8, 2006]. Retrieved from: IEEE Database.
Frey, Jr. Alexander Hamilton
Nanda Sanjeeb
Treadway Tommy Robert
Adaptec, Inc.
Beusse Wolter Sanks Mora & Maire, P.A.
Bragdon Reginald G.
Sartor W. David
Vo Thanh D.
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