Radix-N architecture for deinterleaver-depuncturer block

Details Radix-N architecture for deinterleaver-depuncturer block Radix-N architecture for deinterleaver-depuncturer block

2006-01-31

2006-01-31

Chase, Shelly (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S795000

Reexamination Certificate

active

06993702

ABSTRACT:
A de-interleaver-de-puncturer architecture is scalable and capable of achieving a higher data throughput than that achievable using a conventional disjointed de-interleaver-de-puncturer architecture. The higher data throughput is achieved without increasing the clock speed of the de-interleaver. The scalable de-interleaver-de-puncturer architecture is also less complex than a conventional disjointed de-interleaver-de-puncturer architecture.

REFERENCES:
patent: 5943371 (1999-08-01), Beale et al.
patent: 6335922 (2002-01-01), Tiedemann et al.
patent: 6732326 (2004-05-01), Choi et al.

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