Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-05-25
2003-09-09
Deppe, Betsy L. (Department: 2734)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S371000, C375S373000
Reexamination Certificate
active
06618459
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a radio communication device and a method of accomplishing bit synchronization pull-in or phase follow-up, and more particularly to a selective calling radio-receiver and a method of accomplishing bit synchronization pull-in.
2. Description of the Related Art
FIG. 1
illustrates an example of a conventional radio communication device. The illustrated radio communication device is constituted as a selective calling radio-receiver. The selective calling radio-receiver is comprised of an antenna
101
through which a radio signal is received, a signal-receiving circuit
102
receiving a radio signal from the antenna
101
, and a decoder
103
decoding a radio signal transmitted from the signal-receiving circuit
102
.
A radio signal received through the antenna
101
is demodulated in the signal-receiving circuit
102
, and the thus demodulated signal is transmitted as a demodulated output signal
105
to the decoder
103
.
The decoder
103
is comprised of a clock-generating circuit
106
generating a data-receiving clock, a phase-difference correcting circuit
107
which corrects a phase of the data-receiving clock, a data-receiving circuit
108
which receives the data-receiving clock from the clock-generating circuit
106
, and then, receives the demodulated output signal
105
from the signal-receiving circuit
102
in accordance with the data-receiving clock, and a data-storing memory
109
which stores therein data having been received in the data-receiving circuit
108
.
In a selective calling radio-receiver, synchronization in a phase is generally established between a received signal and a data-receiving clock in order for a data-receiving circuit to receive a signal at an appropriate timing. In the conventional radio communication device illustrated in
FIG. 1
, the above-mentioned synchronization in a phase was conducted by correcting a phase of the data-receiving clock with a certain correction, regardless of a difference in a phase between a received signal or the demodulated output signal
105
.
The synchronization pull-in conducted in the radio communication device illustrated in
FIG. 1
is effective when a difference in a phase between the received signal and the data-receiving clock is greater than the above-mentioned certain correction. However, even when the difference in a phase becomes smaller than a predetermined correction, a correction is kept unchanged, that is, a correction is kept at a fixed value, which reduces accuracy in phase-synchronization.
This problem can be solved to some degree, if a correction is originally designed to have a small value, however, which is accompanied with another problem of reduction in phase following ability.
Japanese Unexamined Patent Publication No. 1-284028 has suggested a selective calling receiver including a circuit which operates a bit synchronization circuit only while a synchronization word signal is being received, after a position of the synchronization word has been detected.
Japanese Patent No. 2535226 (Japanese Unexamined Patent Publication No. 1-136077) has suggested a selective calling receiver comprising a receiver which receives a selective calling signal from a base station and outputs the received signal as a digital signal, a bit synchronization circuit which synchronizes the digital signal to an internal clock generated in an internal oscillation circuit, a frame synchronization signal receiving circuit which receives a frame synchronization signal which is intermittently transmitted thereto, a phase-difference detecting circuit which detects a phase-difference at the outset of signal-receiving, based on an internal phase correction signal transmitted from the bit synchronization circuit, a bit-difference detecting circuit which detects a difference in a bit of internal timing, based on an output transmitted from the frame synchronization signal receiving circuit, a correction determining circuit which determines a correction based on outputs transmitted from the phase-difference detecting circuit and the bit-difference detecting circuit, and a correction circuit making a correction for a frequency of the internal oscillation circuit.
Japanese Unexamined Patent Publication No. 6-152502 has suggested a selective calling radio-receiver comprising a turning point detecting circuit which detects a turning point of a received signal, a timing generator which generates internal standard clock, a phase comparator which calculates a correction for a phase between an output transmitted from the turning point detecting circuit and the internal standard clock, and a variable divider which receives the correction, determines a division ratio of the internal standard clock, and reproduces a clock.
Japanese Unexamined Patent Publication No. 8-8811 has suggested a synchronization establishing apparatus which detects spatial TDMA timing with an accuracy of 1/m symbol, based on a detecting timing of a unique word.
Japanese Unexamined Patent Publication No. 9-36737 has suggested a phase-synchronous circuit including an A/D converter which converts a voltage transmitted from a low-pass filter into a digital signal, a standard value setting circuit in which a level equal to a half of an output level of the A/D converter is determined as a standard level, a comparator which compares an input level transmitted from the A/D converter to the standard level, a programmable multiplier, and a memory storing data used for controlling the programmable multiplier in accordance with a difference between the input level and the standard level.
Japanese Unexamined Patent Publication No. 7-336342 has suggested a clock reproducing circuit including an edge detecting circuit which detects an edge in a received signal and detects synchronization timing included in the received signal, a standard signal generating circuit generating a plurality of standard signals having different phases from one another, but having a common frequency, and an output selecting circuit selecting a standard signal among the plurality of standard signals, which standard signal has a phase closet to synchronization timing included in the received signal, and transmitting the thus selected standard signal as a clock signal. In accordance with the clock reproducing circuit, the clock signal is not gradually synchronized to synchronization timing included in a received signal, but is immediately synchronized to a timing relatively close to the synchronization timing.
Japanese Unexamined Patent Publication No. 6-268700 has suggested a timing reproducing circuit including a first circuit measuring estimated distances between m sample points and a zero-cross point, a second circuit calculating an average among the thus measured estimated distances, a third circuit converting the thus calculated m averages into average distances between rising points of m reproduced clocks and a next zero-cross point, detecting a difference in a phase between fall edges of the reproduced clocks and the zero-cross point, controls a phase in the reproduced clocks at synchronization, and controls an up-down counter based on both upper most bits of the estimated distances and the zero-cross detecting signal, to thereby control a difference in a phase between the zero-cross point of the received signal and the fall edges of the reproduced clocks.
Japanese Unexamined Patent Publication No. 9-135240 has suggested a digital phase-synchronous circuit including an N-bit counter which divides an output transmitted from digital VCO to thereby transmit N divided signals, a selector which switches the divided signals to a symbol clock in response to a switched rate, and an adder positioned between the N-bit counter
6
and the selector
7
. When a rate is switched, a switch transmits phase offset values established in accordance with a plurality of transfer rates, to the adder, and the adder transmits a divided output to the selector.
The above-mentioned Publications are accompanied with the same problem as the probl
Deppe Betsy L.
NEC Corporation
Whitham Curtis & Christofferson, P.C.
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