Radiation tolerant back biased CMOS VLSI

Details Radiation tolerant back biased CMOS VLSI Radiation tolerant back biased CMOS VLSI

2000-01-19

2003-06-24

Picardat, Kevin M. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S350000, C257S372000, C257S401000, C257S402000

Reexamination Certificate

active

06583470

ABSTRACT:

FIELF OF THE INVENTION
This invention relates to integrated circuits. More particularly, this invention relates to a circuit configuration for reducing the impact of total ionizing radiation effects which lead to degradation in performance and overall functionality of CMOS integrated circuits.
BACKGROUND OF THE INVENTION
FIG. 1
shows a cross section of a typical CMOS integrated circuit. The circuit shown and described is a p-well circuit. However, it will be apparent to those of ordinary skill in the art that this discussion also applies to n-well circuits by simply interchanging n-type and p-type structures or twin well circuits.
In
FIG. 1
, an n-type semi-conductor substrate
10
, including an n-channel region
34
and a p-channel region
36
, is provided for forming the integrated circuit thereon. P-channel devices, such as a p-channel transistor M
2
, are formed in the n-type substrate
10
by diffusing or implanting a source
12
and a drain
14
. In the circuit of
FIG. 1
, the source
12
of the transistor M
2
is coupled to a positive voltage supply Vdd. In typical CMOS circuits, a Vdd to substrate contact is formed of an n+ diffusion
16
.
Further, a p-well
18
is formed in the n-type substrate
10
. The exemplary integrated circuit illustrated in
FIG. 1
also includes an n-channel transistor M
1
with a drain
20
and a source
22
formed within the p-well
18
by diffusion or implantation. The source
22
is coupled to ground. A Vss to p-well contact is formed of a p+ diffusion
24
which is also coupled to ground. A p-channel gate
26
of the transistor M
2
is formed over a layer of gate insulating oxide
28
in the p-channel region
36
between the source
12
and the drain
14
. Similarly, a gate
30
is formed on a layer of gate insulating oxide
32
between the drain
20
and the source
22
of the n-channel transistor M
1
in the p-well
18
. This circuit is controlled by a voltage Vin applied to the two gates
26
and
30
. The p-channel drain
14
is electrically coupled to the n-channel drain
20
. The output of this circuit is a signal Vo formed on the two drains
14
and
20
.
FIG. 2
illustrates a more detailed cross section of a typical CMOS integrated circuit. The integrated circuit of
FIG. 2
includes a parasitic field transistor M
3
in addition to the transistors M
1
and M
2
shown in FIG.
1
. The parasitic field transistor M
3
shown in
FIG. 2
is an n-channel transistor and includes a gate
40
formed on a layer of field insulating oxide
38
between the drain
20
and the n+ diffusion
16
.
Ionizing radiation occurs naturally in the form of charged particles that possess enough energy to break atomic bonds and create electron and hole pairs in an absorbing material. These charged particles may include protons, electrons, atomic ions, and photons with energies greater than a bandgap of the absorbing material. When typical integrated circuits, such as the CMOS integrated circuits described above and shown in
FIGS. 1 and 2
, are exposed to the charged particles over a period of months or even years, the ionizing radiation can contribute to a total ionizing dose. The total ionizing dose can have detrimental long term effects on the typical integrated circuit including circuit performance degradation and functional failure.
For example, as the charged particles pass through MOS devices, such as those shown in
FIGS. 1 and 2
, they generate electron and hole pairs which can be trapped in the gate oxides
28
and
32
(
FIGS. 1 and 2
) and the field oxide
38
(FIG.
2
). Mobile electrons quickly transport through the field oxide
38
through the gate oxides
28
and
32
, however, the holes have a low effective mobility and are easily trapped in the gate oxides
28
and
32
and the field oxide
38
. The trapped holes, creating a positive oxide charge, shift threshold voltages of the transistors M
1
, M
2
and M
3
in a negative direction. Further, as the charged particles pass through MOS devices, interface states also increase. This increase in the interface states shifts the threshold voltages in the positive direction for n-channel devices, such as the transistor M
1
and M
3
, and in the negative direction for p-channel devices, such as the transistor M
2
. Generally, the positive oxide charge shift is greater than the interface states shift. As a result, the magnitudes of the threshold voltage of the n-channel transistors M
1
and M
3
decrease while the magnitude of the threshold voltage of the p-channel transistor M
2
increases.
In addition to the positive oxide shift and the interface states shift described above with respect to n-channel and p-channel devices, threshold voltage shifts caused by charged particles further affect parasitic MOS elements, such as the parasitic transistor M
3
of FIG.
2
. For example, as the threshold voltage of parasitic n-channel transistor M
3
decreases, channels begin to form around the drawn n-channel transistor M
1
and leakage currents flow around the edges of the n-channel gate region
30
. Leakage currents begin to flow from the drain
20
to the source
22
. Further, leakage currents also begin to flow from the drain
20
and source regions
22
of the drawn n-channel transistor M
1
to the n-type substrate
10
or the n-well through the parasitic field transistor M
3
. These leakage currents may cause parametric failure to occur before functional failures.
The effects of these charged particles lead to the degradation of performance and ultimate failure of the CMOS devices. The additional radiation-induced interface states degrade the circuit performance by reducing the channel mobility, which as a result decreases channel conductance and transistor gain. Over time, the threshold voltages of the n-channel and p-channel devices may shift to a degree where the n-channel transistors cannot be turned off and the drive capability of the p-channel transistors is not sufficient for the circuit to continue operating at the system clock rate. Such a shift in threshold voltages of either the n-channel or p-channel transistors will cause the circuit to fail.
In addition to the concerns of long term total ionizing dose effects from radiation, there are also concerns of single event effects. Like total ionizing dose effects, single event effects occur because of galactic cosmic rays, solar enhanced particles, and energetic protons and neutrons. However, unlike the total ionizing dose effects, the failure of the circuit due to these single event effects are immediate and do not rely on a cumulative bombardment of charges and the like. Within the scope of single event effects, there are two common categories of single event failures which comprise the following: single event latch up and single event upset.
A first common type of failure is the single event latch up. In CMOS devices containing both n-channel and p-channel devices on a silicon substrate, parasitic bi-polar transistors exist. Latch-up is a well understood and documented phenomenon resulting from parasitic bipolar transistors.
FIG. 3
shows the cross section of the integrated circuit of
FIG. 1
with a pair of parasitic bipolar transistors T
1
and T
2
coupled as a Semiconductor Controlled Rectifier (SCR). The transistor T
1
is a parasitic pnp transistor. The transistor T
2
is a parasitic npn transistor. The emitter of the transistor T
1
is formed of the p+ source diffusion
12
of the p-channel transistor. The base of the transistor T
1
and the collector of the transistor T
2
are formed of the n-type substrate
10
. The collector of the transistor T
1
and the base of the transistor T
2
are formed of the p-well diffusion
18
. The emitter of the transistor T
2
is formed of the n+ source diffusion
22
of the n-channel transistor. A parasitic impedance R
s
is formed in the substrate
10
between the base and the emitter of the parasitic pnp transistor T
1
. A parasitic impedance R
w
is formed in the p-well
18
between the base and emitter of the parasitic npn transistor T
2
.
FIG. 4
shows an equivalent

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