Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2002-05-15
2004-06-01
Elms, Richard (Department: 2824)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S154000, C365S185070, C365S185180
Reexamination Certificate
active
06744661
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to semiconductor memories. More particularly, and not by way of any limitation, the present invention is directed to the design of a radiation-hardened static memory cell having improved immunity to soft errors.
2. Description of Related Art
With the advent of smaller 0.13- and 0.10 &mgr;m semiconductor geometries, and the shift from logic-based to memory-dominant chips, designers must watch out for soft errors. These errors result whenever the charges generated by extraneous sources exceed a critical charge required to flip data stored in a bit cell (i.e., upset event). Common causes of this discharge problem include, for example, &agr;-particle bombardment, metal coupling, and system noise.
Until recently, soft errors were mainly a problem in aerospace applications because these errors increase with altitude and exposure to radiation. That is no longer the case with the spread of memory technology into commercial, consumer, and industrial applications, where downtime caused by soft errors can be very costly.
Except for dynamic random access memories or DRAMs, memory cells in geometries larger than very deep submicron (VDSM) line widths have been known to be relatively insensitive to &agr;-particle radiation. On the other hand, DRAMs designed in 0.13 &mgr;m or smaller technologies are very susceptible to soft errors. Even static random access memories SRAMs are becoming sensitive to soft errors because of their small memory bit cells, where a logic state of 0 or 1 is represented by a very small charge.
Sources of harmful radiation can vary greatly depending on the application. For example, a chip's packaging, or just cosmic radiation, can generate &agr; particles. These are doubly ionized helium particles that can penetrate 20 to 30 &mgr;m of Silicon and create electron-hole pairs. A single a particle can generate as many as a million electron-hole pairs for a penetration of about 25 &mgr;m into Silicon.
With memory cells being so small at the VDSM geometries seen today, these electron-hole pairs can accumulate to create a charge that disrupts stored information. The amount of charge that represents a bit value in a 0.13 &mgr;m SRAM cell is about {fraction (1/16)} of what is required in 0.25 &mgr;m geometries, making the cells almost an order of magnitude more susceptible. DRAMs, however, have always had less charge and been more vulnerable to soft errors, even before the advent of VDSM technology.
Failure rates due to soft errors are measured as Failures in Time (FITs). An FIT is one failure in a billion hours. In a system with 50 components, if the system can only fail once a year, every component must meet a design specification of 2281 FITs. Fortunately, soft errors can be prevented or corrected because, although there's data loss, there's no damage to the underlying memory devices. Through advancements in packaging, memory design, and process techniques, soft-error rates from alpha-particle bombardment can be avoided. In packaging, the use of special radiation-absorbing die coats, materials with lower lead content (lead emits &agr; particles), and keeping the bumps in a ball-grid array (BGA) away from the memory are all very effective ways to reduce soft errors.
Memory design techniques can be improved to reduce soft errors as well. Increasing transistor size will increase cell storage capacitance, and adding RC delays can increase cell-flip times. Some of the other design hardening techniques are based on storage latch duplication and use state-restoring feedback delays. Whereas the current design techniques could represent a viable alternative to achieve upset immunity in submicron CMOS designs, unfortunately they are beset with several drawbacks that make them inapplicable to high density circuit architectures: high area overhead, high power dissipation (due to the use of NMOS and/or PMOS inverters, with inherently high leakage currents) and critically-ratioed transistor sizing in order to achieve upset immunity.
SUMMARY OF THE INVENTION
Accordingly, the present invention advantageously provides a static memory cell having reduced susceptibility to soft error events, wherein data storage nodes are hardened by way of junction isolation. In one implementation, the memory cell is preferably provided to be an 8T SRAM device. A first inverter is formed with a first N-channel Metal Oxide Semiconductor (NMOS) device and a first P-channel MOS (PMOS) device, with a first isolation device disposed therebetween. A second inverter is cross-coupled to the first inverter to form a pair of data storage nodes therein. The second inverter is also provided with a second isolation device disposed between its pair of NMOS and PMOS devices. A first data storage node is formed at a coupling between the first PMOS device and the first isolation device and a second data storage node is formed at a coupling between the second PMOS device and the second isolation device. In a presently preferred exemplary embodiment, the isolation devices are comprised of PMOS devices, whereby all-PMOS data storage nodes are obtained. The N-well junctions of the PMOS devices help harden the data nodes against a soft error event such as, e.g., radiation.
As a further variation, the present invention provides an 8T SPAM cell having two or more access ports. Each of the two complementary data storage nodes is coupled to an equal number of access devices, wherein each pair (one coupled to one data storage node and the other coupled to the complementary data storage node) is operable as a separate access port.
In another aspect, the present invention is directed to a register file cell having reduced susceptibility to soft error events. The register file cell preferably comprises a hardened static memory cell such as the 8T memory cell set forth above. A separate read and write ports are provided for supporting dual port access to the data nodes. In further implementations, two or more read ports may be provided.
The PMOS isolation devices can be operable in various modes under different biasing conditions. In one exemplary implementation, the gates of the PMOS isolation devices are coupled to V
SS
. In another implementation, the gates are biased at a predetermined negative voltage level, e.g., at around −0.5V to −1.0V. In a still further implementation, the PMOS isolation devices may be provided as depletion mode devices.
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Danamraj & Youst P.C.
Elms Richard
Le Toan
Virage Logic Corp.
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