Radiation hardened logic circuits

Details Radiation hardened logic circuits Radiation hardened logic circuits

2007-10-29

2009-10-06

Chang, Daniel D (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar and fet

C326S023000, C326S083000, C326S084000

Reexamination Certificate

active

07598773

ABSTRACT:
A radiation hardened inverter includes first and second electrical paths between an input terminal and an output terminal. A first PFET is disposed in the first electrical path, and a bipolar junction transistor (BJT) is disposed in the second electrical path. The first PFET is configured to convert a low level signal at the input terminal to a high level signal at the output terminal, and the BJT is configured to convert a high level signal at the input terminal to a low level signal at the output terminal. The radiation hardened inverter includes a second PFET disposed in the second electrical path. The second PFET is configured to provide a path for bleeding excess current away from the BJT. The radiation hardened inverter also includes a current limiting PFET disposed in the second electrical path. The current limiting PFET is configured to limit current flowing into a base of the BJT. The radiation hardened inverter is free-of any NFETs.

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Q. Zhou et al., “Cost-Effective Radiation Hardening Technique for Combinational Logic”, IEEE, 2004, pp. 100-106.
D. C. Mayer et al., “Designing Integrated Circuits to Withstand Space Radiation”, Crosslink, 2003.

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