Radiation hardened dielectric for EEPROM

Details Radiation hardened dielectric for EEPROM Radiation hardened dielectric for EEPROM

1998-04-16

2000-10-10

Niebling, John F.

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438953, 438778, 438784, 438785, 438257, 438261, 438286, 438299, 438301, 438302, 257651, H01L 2131

Patent

active

061301728

ABSTRACT:
A EEPROM 140 has a storage transistor 160 with a gate insulating layer 104 of BPSG and a polysilicon gate 112.2 of the same layer as the polysilicon gate 112.1 of the FET transistor 150. The BPSG layer 104 has POHC traps that capture holes injected into N well 103.2. A positive voltage applied to N well 103.2 programs the storage transistor 160 off. Applying a positive voltage to the gate 112.2 neutralizes the holes stored in layer 104 and erases the memory of transistor 160.

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S. Rojas et al. J. Vac. Sci. Tech. B. 10(2), p. 633, Mar. 1992.

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