Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Charge transfer device
Reexamination Certificate
1996-09-03
2002-08-27
Chaudhari, Chandra (Department: 1104)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Charge transfer device
C438S060000, C438S200000
Reexamination Certificate
active
06440782
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to silicon semiconductor devices of the complementary metal-oxide semiconductor (CMOS) type. More particularly, the present invention relates to such silicon-based CMOS devices which include a charge coupled device (CCD), which operate at cryogenic temperatures, and which are radiation-hard.
2. Related Technology
Complementary metal-oxide semiconductor (CMOS) technology is so-named because it uses both p-type and n-type metal-oxide semiconductor field-effect transistors in its circuits. CMOS is widely used in circuits in which low power consumption is important. CMOS is also used in circuits where very high noise margins are important (e.g., in radiation-hard circuits).
With the development of very large-scale integration (VLSI) circuits, power consumption in conventional n-type metal-oxide semiconductor (NMOS) circuits began to exceed acceptable limits. A lower-power technology was needed to exploit the VLSI fabrication techniques. CMOS represented such a technology. From 1968 to 1987, a 200-fold increase in functional density and a 20-fold increase in speed of CMOS VLSI integrated circuits took place. One example of this tremendous increase in density is the Intel 4004 4-bit microprocessor which in 1971 had 2,300 devices. By 1985, the well-known Intel 80386 16-bit processor had 275,000 devices.
In CMOS technologies, both n-channel and p-channel transistors must be fabricated on the same wafer. However, only one type of device can be fabricated on a given starting semiconductor substrate itself, because this substrate is doped with an n-type or p-type impurity. In order to achieve the other type of device that cannot be built in a particular substrate type itself, regions of the substrate are subjected to a doping type opposite to that present in the starting substrate material. This opposite doping is sufficient to change the type of the material to the opposite type. These regions of opposite doping (generally called wells) are among the first features to be defined in a processing wafer. This well formation is generally done by implanting and diffusing an appropriate dopant to attain the proper well depth and doping profile. The doping type of the wells becomes the identifying characteristic of a CMOS device.
Current radiation-hard cryo-CMOS devices include a very thin re-oxidized nitride-oxide (RONO) layer of about 120 Å thickness under the first polysilicon gate for the focal plane array readout circuitry (i.e., for the charge transfer structure used by the focal plane array device to control electrical charges indicative of photon flux at a particular photo-responsive receptor). The standard anisotropic plasma etch process, which is conventionally used for accurate gate definition without undercutting, for active devices formed in part by the first polysilicon layer will also attack and damage the RONO layer. Consequently, this RONO layer will not be an acceptable gate oxide layer even after a second oxidation step is performed for the gates defined by the second polysilicon layer. Accordingly, a CCD device requiring a good gate oxide under the second polysilicon gates can not be fabricated using the conventional technology.
SUMMARY OF THE INVENTION
In view of the deficiencies of conventional cryo-CMOS technology, an object for this invention is to avoid one or more of these deficiencies.
Many new applications for cryo-CMOS devices with CCD's require active device channel lengths to be in the sub-micron range (i.e., less than 1 &mgr;m) in order both to increase the speed of the devices, and to increase packing density and read-out resolution. These increased requirements are desirable while maintaining the same low-temperature radiation hardness and device performance.
Accordingly, it is an object of the present invention to provide a cryo-CMOS process which produces a radiation-hard cryo-CMOS device with ccD's, and with channel lengths in the sub-micron region without experiencing any degradation in the device radiation-hardness or the device performance.
Another object for the present invention is to provide such a cryo-CMOS process and device including CCD's, with a radiation-hardness greater than 10
5
rads (Si).
Particularly, it is an object for this invention to provide a cryo-CMOS process and device including CCD's, with a radiation-hardness good to 1×10
6
rads (Si).
According to one aspect of the present invention, a method of fabricating a silicon-based radiation-hard cryogenic complementary metal oxide semiconductor (cryo-CMOS) charge-coupled device (CCD) includes sequential steps of: providing a silicon substrate; forming a pair of adjacent wells of opposite doping type in the substrate, and an adjacent CCD area; providing a layer of re-oxidized nitride/oxide over the CCD area; providing a layer of polysilicon over the layer of re-oxidized nitride/oxide, over the pair of adjacent wells and the adjacent CCD area; plasma etching the layer of polysilicon at the pair of wells to define a respective pair of gates for transistors to be formed in the pair of wells; and simultaneously protecting the layer of polysilicon and re-oxidized nitride/oxide over the CCD area so that both are substantially not affected by the plasma etching; and wet-chemical etching the layer of polysilicon over the CCD area to form CCD first polysilicon gates, while substantially not attacking the re-oxidized nitride/oxide layer at the CCD area with the wet-chemical etch.
According to another aspect, the present invention provides a silicon-based radiation-hard cryogenic complementary metal oxide semiconductor (cryo-CMOS) charge-coupled device (CCD) including: a silicon substrate; a pair of adjacent wells of opposite type formed in the substrate; a CCD area in the substrate adjacent to the pair of wells; a thin re-oxidized nitride/oxide layer over the CCD area which has not been compromised by exposure to plasma etching; a CCD gates formed on the re-oxidized nitride/oxide layer at the CCD area; and a CCD charge transfer control structure formed at the CCD area in association with the pair of CCD gates.
Another aspect of the present invention is that the p
+
channel stop is heavily doped to a level at which threshold voltage is significantly increased, preferably by a factor of approximately 20. Therefore, after a high-level radiation dose, the n-channel field threshold voltage will still maintain a desired level above the normal operation voltage to avoid turn-on of the n-channel field devices.
One of the advantages of the radiation-hard CMOS process of the present invention is that the channel length of the device can be significantly reduced to less than one &mgr;m without any degradation in the CCD performance, or device radiation-hardness. Further, with a significantly reduced channel length, the speed of the device is increased, packing density is improved, and read-out resolution is also improved while maintaining low-temperature radiation-hardness and CCD performance.
Another advantage of the present device and process is that the first CCD gate formed by a polysilicon
1
layer, and a second CCD gate formed by a polysilicon
2
layer both have the same thin layer of re-oxidized nitride/oxide (RONO) layer underneath. Accordingly, these devices should be good to at least 1×10
6
rads (Si) without failure because of radiation.
Other aspects, features, and advantages of the present invention will become apparent to those ordinarily skilled in the pertinent arts from a reading of the following detailed description of a singular exemplary preferred embodiment with reference to the accompanying drawings, in which the same reference numerals are used to indicate the same features, or features which are analogous in structure or function, throughout the several drawing Figures.
REFERENCES:
patent: 5369039 (1994-11-01), Hynecek
patent: 5489545 (1996-02-01), Taguchi
patent: 5500383 (1996-03-01), Hynecek
Cable James S.
Chang Chen-Chi P.
Alkov Leonard A.
Chaudhari Chandra
Hughes Electronics
Lenzen, Jr. Glenn H.
Schubert William C.
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