Radial arm memory bus for a high availability computer system

Details Radial arm memory bus for a high availability computer system Radial arm memory bus for a high availability computer system

1999-10-28

2003-03-04

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C365S230060, C365S189050

Reexamination Certificate

active

06530033

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to providing a high speed bus for a memory system, and more specifically provides a memory system for high availability servers where the speed of transactions on the bus is increased by reducing the effective capacitance of the bus and where high availability features are enabled by the improved isolation between memory modules.
2. Description of the Related Art
As computers and their central processing units (“CPUs”) become capable of executing instructions more rapidly, there is a concurrent need for increased processing speed of memory instructions. In performing a typical data read operation of a memory device, a memory controller (usually the CPU or, in larger systems, a dedicated memory controller) sends a read command to a particular memory chip. This command is propagated to the chip along one or more lines of a command bus. When received by the particular chip, the command causes the chip to locate and direct an output from its internal memory array onto a data bus, as a return data signal intended for the memory controller. The output then propagates along the data bus, which may or may not travel the same route as the command bus. In the example just given, there are three sources of time delay, including the propagation time of a read command from the controller to the chip, the time required for the chip to power its internal registers and to channel the proper output onto the data bus, and the time required for propagation of the output back to the controller.
Similarly, in performing a typical data write operation to a memory device, the memory controller sends a write command to a particular memory chip along with the data to be written. This command is propagated to the chip along one or more lines of a command bus, while the data is propagated to the chip along one or more line of a data bus. When received by the particular chip, the command causes the chip to channel the data from the data bus to the specified location of its internal memory array. The data propagating along the data bus may or may not travel the same route as the command propagating along the command bus. In the example just given, there are three sources of time delay, including the propagation time of a write command from the controller to the chip, the time required for propagation of the data from the controller, and the time required for the chip to power its internal registers and to channel the data from the data bus.
Typically, design efforts have focused primarily on improving internal routing and processing of instructions within memory chips. These design efforts, however, while continually providing more responsive memory devices, do not address the primary cause of propagation delay along the data bus, the inherent capacitance of the data bus. As a result, many systems are sending data over the data bus at rates far lower than the operating speeds of the CPUs.
The problem of inherent capacitance of the data bus is further explained with reference to
FIGS. 1A and 1B
.
FIGS. 1A and 1B
illustrates a data path within a memory system
100
. The memory system
100
shown is configured for either a SDR (Single Data Rate) or DDR (Double Data Rate) SDRAM memory system. The data path includes a memory controller
102
, a motherboard
103
, memory chips
104
, memory modules
105
, and a data bus
106
. The data bus
106
includes board trace portions
107
, module trace portions
108
, connectors
109
, and termination
110
.
The memory controller is affixed to the motherboard and is electrically connected to the memory chips via the data bus such that the memory modules are connected in parallel. The memory chips are affixed to the memory modules. The board trace portion of the data bus is affixed to the motherboard and the module trace portion of the data bus is affixed to the memory modules. The connectors
109
electrically connect the board trace portions to the module trace portions and mechanically affix the memory modules to the motherboard.
FIG. 1B
depicts the electrical equivalent
111
of the data path shown in FIG.
1
A. For ease of reference, each electrical equivalent in
FIG. 1B
that represents a component shown in
FIG. 1A
is labeled with the reference numeral of the represented component with the suffix “A”. It should be noted that the board trace portion
107
A is made up of inductive and capacitive elements which together behave as a transmission line
112
having a set of impedance and transmission delay characteristics. Similarly, each of the module trace portions
108
A are made up of inductive and capacitive elements which together behave as transmission lines
113
, each having its own set of impedance and transmission delay characteristics.
When properly terminated with a resistor
110
A, the board trace portion
107
A acts as a nearly perfect transmission line (not shown) without inherent capacitance and will not in and of itself limit the operating speed of the memory system. When combined with the module trace portions
108
A, however, the module trace portions
113
act as transmission line stubs coming off of the board trace portion
107
A. These stubs together have a “comb filter” effect that includes significant signal reflections in the memory system that decreases signal integrity. This “comb filter” effect imposes a load on the data bus and effectively breaks the board trace portion
107
A into individual board trace portion transmission lines
113
.
The load imposed by the “comb filter” effect limits the maximum transmission speed of data propagation in both the board trace portion
107
A and the module trace portions
108
A. The “comb filter” effect imposed by the stubs generally increases as the length of each the module trace portions
108
A increases. Similarly, the “comb filter” effect imposed by the stubs generally decreases as the length of each of the module trace portions
108
A decreases. A second cause of the propagation delays for data signals sent from the memory controller
102
A to the memory chips
104
A are the inductive element
114
and capacitive element
115
associated with each memory chip. Together, the inductive and capacitive elements impose a capacitive load on the data bus including both the module trace portions
108
A and the board trace portion
107
A. The load imposed by the “comb filter” effect and the capacitive load imposed by the memory chip elements together form the inherent distributed capacitance load on the memory bus.
Another common memory configuration for computer memory systems is the RAMBUS memory configuration.
FIG. 2
shows a schematic diagram illustrating the electrical equivalent of a the data path of a conventional RAMBUS memory system. The data path includes a memory controller
202
, memory modules
205
, and data bus
206
. The data bus includes board trace portions
207
, module trace portions
208
, connectors
209
, and termination resistors
210
. Unlike the memory configuration shown in
FIGS. 1A and 1B
where the memory modules are connected in parallel, in the RAMBUS configuration shown in
FIG. 2
, the memory modules are connected in series. In addition, the connector inductive element
209
occurs at twice as often as the equivalent memory configuration shown in
FIGS. 1A and 1B
that has the same number of memory modules.
The board trace portion
207
is made of inductive and capacitive elements which together behave as a transmission line having a set of impedance and transmission delay characteristics. Similarly, each of the module trace portions
208
are made up of inductive and capacitive elements which together behave as transmission lines
213
, each having its own set of impedance and transmission delay characteristics. When combined with the module trace portions
208
, however, the module trace portions
213
act as transmission line stubs coming off of the board trace portion
207
decreasing signal speed and integrity.
Compared to the configuration shown in
FIG. 2
, the configuration shown

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