Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-05-01
2004-06-08
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S328000, C257S335000, C257S341000
Reexamination Certificate
active
06747312
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to MOSFET devices and more specifically relates to a MOSFET for operation in a high radiation environment and the process for its manufacture.
BACKGROUND OF THE INVENTION
Power MOSFETs are well known and processes for the manufacture of MOSFETs which are operable in high radiation [megarad ionizing radiation] environments are also known. Thus, it is known that a “late gate” which is a non-self aligned gate relative to an invertible channel region, should be used in the manufacture of such devices, known as Rad Hard (radiation hardened) devices. By using a late gate process, the gate oxide is not subjected to the high diffusion temperatures used for the diffusion of base and source regions. The exposure of the gate oxide to such high temperatures reduces the ability of the device to operate in a high radiation environment such as that experienced at very high altitudes or by orbiting space vehicles. Such processes are described in U.S. Pat. No. 5,338,693 in the name of Kyle Spring et al.; U.S. Pat. No. 5,475,252 in the name of Kyle Spring et al.; U.S. Pat. No. 5,831,318 in the name of Perry Merrill; and U.S. Ser. No. 09/263,916 in the name of Milton Boden et al. describe this problem and propose respective solutions.
The topology employed for Rad Hard devices may be cellular, but in some cases, such as for low voltage MOSFETs with a low gate capacitance it is also known that a stripe geometry is preferred, as described in U.S. Ser. No. 09/263,916.
Many MOSFET applications have the required condition of high voltage (in excess of about 25 volts), and low R
DSON
. It is known that the R
DSON
of a cellular MOSFET can be reduced by an increasing (often termed enhancing) the conductivity in the JFET region between spaced bases. This reduces the efficiency of the inherent JFET region and reduces the pinch-off of the region by reducing the expansion of the depletion regions from the spaced bases forming the JFET. This type of enhanced conductivity region and the process for its formation are described in U.S. Pat. Nos. 4,376,286; 4,593,302 and 4,680,853, in the names of Lidow and Herman. These patents do not disclose or suggest how such an enhancement can be applied to a Rad Hard type device.
All vertical conduction MOSFET devices have an inherent or parasitic body diode. This diode is formed by the junction between the channel diffusion, which is P type for an N channel device and the N
−
junction receiving layer. This structure is an abrupt junction and turns off relatively quickly, creating high voltage surges in an inductive circuit. Further, a relatively high avalanche current will flow in the series circuit including the relatively high conductivity P channel region (in an N channel device). It would be desirable to modify the characteristics of the body diode to offset these characteristics.
BRIEF SUMMARY OF THE INVENTION
The present invention is for a novel structure and process for its manufacture of a high voltage N or P channel Rad Hard MOSFET which has a reduced Q
g
and R
DSON
. To obtain these conflicting requirements, a linear stripe geometry is used with a fine polysilicon gate line width of about 3.2&mgr; and a very close spacing of about 2.2&mgr;. The use of this close spacing permits the increase of the number of stripes (or cells) per unit area and thus increases the total channel width. The JFET pinch is then reduced by a novel masked enhancement implant through a very narrow window about 0.6&mgr; (in contrast to the blanket implant of U.S. Pat. No. 4,593,302). This heavily doped enhancement region creates a heavily doped cylindrically shaped region in the parasitic JFET. Thus, R
DSON
is further considerably reduced.
A further important feature of the invention is the novel modification of the body diode structure by grading its concentration; that is, by reducing concentration drastically with depth of the channel diffusion. In a preferred embodiment, this is accomplished by adding a low concentration, but very deep body diffusion at the beginning of the manufacturing process, followed by the conventional formation of a shallower, higher concentration channel diffusion. The result is a highly graded body diode which will have softer turn off characteristics. Further, the lower concentration portion of the diode will be in series with avalanche current and will therefore limit avalanche current magnitude to better protect the device in avalanche. The graded junction also provides a reduction in the source-drain capacitance at low drain source bias.
REFERENCES:
patent: 4593302 (1986-06-01), Lidow et al.
patent: 5322804 (1994-06-01), Beasom
patent: 5338693 (1994-08-01), Kinzer et al.
patent: 5475252 (1995-12-01), Merrill et al.
patent: 5541435 (1996-07-01), Beasom
patent: 5770880 (1998-06-01), Woodbury et al.
patent: 5831318 (1998-11-01), Spring et al.
patent: 2003/0197220 (2003-10-01), Disney
International Rectifier Corporation
Ostrolenk Faber Gerb & Soffen, LLP
Quach T. N.
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