Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2005-11-04
2010-06-15
Shah, Sanjiv (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S156000, C711S203000, C711S204000, C711S205000, C711S207000, C711S208000
Reexamination Certificate
active
07739476
ABSTRACT:
In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.
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Gunna Ramesh
Pan Jesse
Apple Inc.
Dillon Samuel
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Shah Sanjiv
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