Electronic digital logic circuitry – Reliability
Reexamination Certificate
2002-09-16
2004-04-13
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Reliability
C326S011000, C326S014000
Reexamination Certificate
active
06720793
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to programmable logic devices (PLDs) subject to single event upsets. More particularly, the invention relates to structures and methods of generating high reliability designs for PLDs on which single event upsets have minimal impact.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The various logic blocks are interconnected by a programmable interconnect structure that includes a large number of programmable interconnect lines (e.g., metal wires). The interconnect lines and logic blocks are interconnected using programmable interconnect points (PIPs). A PIP can be, for example, a CMOS passgate. When the passgate is turned on (i.e., the PIP is enabled), the two nodes on either side of the passgate are electrically connected. When the passgate is turned off (i.e., the PIP is disabled), the two nodes are isolated from each other. Thus, by controlling the values on the gate terminals of the PIPs, circuit connections can be easily made and altered.
PIPs can be implemented in many different ways. For example, a buffered PIP can be implemented as a tristate buffer. When the tristate signal is low, the buffer output is not driven, and the two nodes on either side of the buffer are isolated. When the tristate signal is high, one of the nodes drives the other node in a unidirectional connection.
Various exemplary types of PIPs are described by Freeman in U.S. Pat. No. Re. 34,363, by Carter in U.S. Pat. Nos. 4,695,740 and 4,713,557, by Hsieh in U.S. Pat. No. 4,835,418, and by Young in U.S. Pat. No. 5,517,135, all of which are hereby incorporated by reference. Some PIPs are unidirectional and some are bidirectional. Some are buffered and some are not buffered. However, the various types of PIPs typically have this in common, that they are controlled by a single data value stored in a memory cell called a configuration memory cell.
The logic blocks and PIPs in a PLD are typically programmed (configured) by loading configuration data into thousands of configuration memory cells that define how the CLBs, IOBs, and interconnect lines are configured and interconnected. In Field Programmable Gate Arrays (FPGAs), for example, each configuration memory cell is implemented as a static RAM cell.
When subjected to unusual conditions such as cosmic rays or bombardment by neutrons or alpha particles, a static RAM cell can change state. For example, a stored high value can be inadvertently changed to a low value, and vice versa. Sometimes these “single event upsets” have no effect on the functionality of the chip. At other times, a single event upset can change the function of a PLD such that the circuit no longer functions properly.
FIG. 1
shows a portion of a PLD that includes three logic blocks LB
1
-LB
3
, five interconnect lines IL
0
-IL
4
, and four PIPs P
1
-P
4
. Interconnect lines IL
1
-IL
3
are coupled to logic blocks LB
1
-LB
3
, respectively. For simplicity, interconnect lines IL
1
-IL
3
are shown directly connected to the corresponding logic blocks. In practice, the interconnect lines do not necessarily connect directly to the logic blocks, but can pass through additional PIPs to reach the logic blocks. Interconnect lines IL
1
-IL
3
can each be programmably coupled to interconnect line IL
0
through PIPs P
1
-P
3
, respectively. Interconnect line IL
4
can be programmably coupled to interconnect line IL
3
through PIP P
4
.
PIPs P
1
-P
4
are respectively controlled by four memory cells MC
1
-MC
4
. When the value stored in one of the memory cells is high, the passgate in the associated PIP is enabled. When the value stored in one of the memory cells is low, the interconnect lines on either side of the associated PIP are not connected together. They can be left unconnected or wired as parts of two separate circuits.
As an example, consider the case where memory cells MC
1
, MC
2
, and MC
4
each store a high value and memory cell MC
3
stores a low value. PIPs P
1
and P
2
are enabled, connecting together interconnect lines IL
1
, IL
0
, and IL
2
. PIP P
4
is also enabled, connecting together interconnect lines IL
3
and IL
4
. PIP P
3
is disabled. Further consider that logic block LB
1
is driving a signal on interconnect line IL
1
and logic block LB
3
is driving a signal on interconnect line IL
3
. For example, PIPs P
1
and P
3
can be included in output drivers of the CLBs including logic blocks LB
1
and LB
3
, respectively. PIPs P
1
-P
4
can also form part of multiplexer structures within logic blocks or CLBs, or within the programmable interconnect structure of the PLD.
Now suppose a single event upset occurs at memory cell MC
1
, and the value stored in memory cell MC
1
changes from a high value to a low value. PIP P
1
is inadvertently disabled, and interconnect line IL
1
is isolated from interconnect line IL
0
. If logic block LB
1
was driving logic block LB
2
through interconnect line IL
0
, for example, the connection no longer exists, and the circuit does not function properly.
Suppose instead that a single event upset occurs at memory cell MC
3
and the value stored in memory cell MC
3
changes from a low value to a high value. PIP P
3
is inadvertently enabled. Logic block LB
3
tries to place a value on interconnect line IL
0
, which is already driven by logic block LB
1
. Contention occurs, which can cause a number of problems ranging from excessive current consumption to a malfunctioning circuit to causing actual damage to the PLD.
Circuits and methods have been developed to avoid the problems associated with single event upsets in non-programmable circuits. One strategy for avoiding such problems is illustrated in FIG.
2
. The illustrated circuit is called a triple modular redundancy (TMR) circuit. In essence, the required logic is implemented three times (i.e., in three modules), and the results generated by the three modules are compared. The two that are the same are considered to be correct, and the “dissenting vote” is thrown out.
The TMR circuit of
FIG. 2
includes modules M
1
-M
3
, representing three implementations of the same logical function. Each module has a respective output signal
01
-
03
that drives voting circuit VC
3
. Voting circuit VC
3
implements the function (
01
AND
02
) OR (
02
AND
03
) OR (
01
AND
03
) and provides the result as the output signal OUT of the circuit.
Clearly, this approach overcomes any single event upset that affects the functionality of one of the three modules M
1
-M
3
. The module affected by the event produces an incorrect answer, which is overridden in the voting circuit by the other two modules.
Kwak and Kim extend the TMR concept to embrace time-multiplexed modular redundancy in “Task-Scheduling Strategies for Reliable TMR Controllers Using Task Grouping and Assignment”, published in the December 2000 issue of IEEE Transactions on Reliability, Vol. 49, No. 4, pages 355-362, which pages are hereby incorporated by reference. Kwak and Kim address the effects of transient errors, rather than permanent errors such as those caused in PLDs by single event upsets. When addressing transient errors, sequentially recalculating a module output, even using the same module, can give different results that can then be resolved by the voting circuit.
In Kwak and Kim's approach, three modules are included in the circuit, but module output values are calculated five times (TMR-Q) using timing rotation in the three modules. A voting circuit determines the “majority vote” for the module output values. Additional calculations can be performed, i.e., N calculations where N is an odd number greater than five (TMR-N).
All of the above methods (TMR, TMR-Q, and TM
Cartier Lois D.
Tran Anh
Xilinx , Inc.
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