Quiet column decoder

Details Quiet column decoder Quiet column decoder

1979-03-12

1980-04-29

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

307238, 365203, 365206, G11C 1140, G11C 1300

Patent

active

042009170

ABSTRACT:
A quiet column decoder is provided which is useful in semiconductor memory systems. The quiet column decoder prevents glitches from being coupled into the silicon substrate during the period of time that the sense amplifiers are sensing data on the bit sense lines. The quiet column decoder has double clocked NOR gates which allows the address lines to be continuous non-multiplexed lines. The double clocked NOR gate has two transistors for precharging a first and a second node within the NOR gate. Another transistor is coupled between the second node and a voltage reference terminal to serve as an enabling device for the NOR gate. The first node of the NOR gate serves as an output for the column decoder.

REFERENCES:
patent: 4136292 (1979-01-01), Suzuki et al.

Affiliated with

Also associated with

Rating

Quiet column decoder does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Quiet column decoder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Quiet column decoder will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1686422