Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Patent
1998-06-16
2000-05-02
Lee, Thomas C.
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
710 10, 710 16, 710 17, 710118, 710125, 710240, G06F 1342, G06F 1336
Patent
active
06058436&
ABSTRACT:
An SCSI quick arbitration and select protocol reduces the timing overhead associated with multiple, sequential data transfer operations, thereby significantly increasing bus efficiencies and average throughput. The conventional arbitration and selection phases are collapsed into a quick arbitrated and select phase, whereby the current SCSI target hosts an arbitration proceeding without the bus transitioning to a bus free phase. The quick arbitrate and select phase is invoked by a current target device by broadcasting a QAS message code during the message-in phase of the current process. QAS capable devices snoop the bus, recognize the QAS message code and enter a quick arbitrate and select phase. A fairness algorithm grants control of the bus to a participating QAS target with the next lowest SCSI ID from that of the current QAS target.
REFERENCES:
patent: 5204591 (1993-04-01), Kaitandjian et al.
patent: 5257356 (1993-10-01), Brockmann et al.
patent: 5613076 (1997-03-01), Latif et al.
patent: 5845154 (1998-12-01), Krakirian
Adaptec, Inc.
Lee Thomas C.
Park Ilwoo
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