Queuing system using dual receive FIFO

Details Queuing system using dual receive FIFO Queuing system using dual receive FIFO

2005-09-13

2005-09-13

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S052000, C710S054000

Reexamination Certificate

active

06944688

ABSTRACT:
A queuing system utilizing dual first-in, first-out (FIFO) memories is provided. The present queuing system is configured to use a first FIFO memory to receive and transfer a plurality of frames to a second FIFO memory wherein the frames include encrypted frame contents. The first FIFO memory is configured to transfer an interrupt to an associated processor in response to completion of the receipt of a valid frame. Next, the processor is configured to reinitialize the first FIFO memory for receipt of a subsequent frame.Additionally, the second FIFO memory is suitably adapted to concurrently store a plurality of frames transferred from the first FIFO memory. Finally, the present system is configured to transfer one of the stored frames out of the second FIFO memory in response to the completion of a data processing operation (e.g. initialization of a decryption algorithm).

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