Queuing cache for vectors with elements in predictable order

Details Queuing cache for vectors with elements in predictable order Queuing cache for vectors with elements in predictable order

2007-07-17

2007-07-17

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S134000, C711S135000, C711S137000

Reexamination Certificate

active

10993972

ABSTRACT:
A cache for storing data elements is disclosed. The cache includes a cache memory having one or more lines and one or more cache line counters, each associated with a line of the cache memory. In operation, a cache line counter of the one or more of cache line counters is incremented when a request is received to prefetch a data element into the cache memory and is decremented when the data element is consumed. Optionally, one or more reference queues may be used to store the locations of data elements in the cache memory. In one embodiment, data cannot be evicted from cache lines unless the associated cache line counters indicate that the prefetched data has been consumed.

REFERENCES:
patent: 5721865 (1998-02-01), Shintani et al.
patent: 5896517 (1999-04-01), Wilson
patent: 6202130 (2001-03-01), Scales, III et al.
patent: 2005/0076181 (2005-04-01), Hsu

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