Queuing and aligning data

Details Queuing and aligning data Queuing and aligning data

2007-08-07

2007-08-07

Elmore, Stephen C. (Department: 2185)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S103000, C711S104000, C711S154000, C711S158000, C341S100000, C341S101000, C365S194000

Reexamination Certificate

active

11072106

ABSTRACT:
Queuing and ordering data is described. Data is stored or queued in concatenated memories where each of the memories has a respective set of data out ports. An aligner having multiplexers arranged in a lane sequence are coupled to each set of the data out ports. A virtual-to-physical address translator is configured to translate a virtual address to provide physical addresses and select signals, where the physical addresses are locations of at least a portion of data words of a cell stored in the concatenated memories in successive order. The multiplexers are coupled to receive the select signals as control select signaling to align the at least one data word obtained from each of the concatenated memories for lane aligned output from the aligner.

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