Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-08-24
2001-09-04
Etienne, Ario (Department: 2155)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S113000, C710S116000, C710S039000
Reexamination Certificate
active
06286068
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application for patent is related to the following applications for patent filed concurrently herewith:
EFFICIENT ADDRESS TRANSFER TECHNIQUE FOR A DATA PROCESSING SYSTEM, Ser. No. 08/317,007, issued as U.S. Pat. No. 5,687,327;
DUAL LATENCY STATUS AND COHERENCY REPORTING FOR A MULTIPROCESSING SYSTEM, Ser. No. 08/316,980, issued as U.S. Pat. No. 5,608,878;
SYSTEM AND METHOD FOR DETERMINING SOURCE OF DATA IN A SYSTEM WITH INTERVENING CACHES, Ser. No. 08/317,256;
METHOD AND APPARATUS FOR REMOTE RETRY IN A DATA PROCESSING SYSTEM, Ser. No. 08/316,978;
ARRAY CLOCKING METHOD AND APPARATUS FOR INPUT/OUTPUT SUBSYSTEMS, Ser. No. 08/316,976;
DATA PROCESSING SYSTEM HAVING DEMAND BASED WRITE THROUGH CACHE WITH ENFORCED ORDERING, Ser. No. 08/316,979;
COHERENCY AND SYNCHRONIZATION MECHANISMS FOR I/O CHANNEL CONTROLLERS IN A DATA PROCESSING SYSTEM, Ser. No. 08/316,977, issued as U.S. Pat. No. 5,613,153;
ALTERNATING DATA VALID CONTROL SIGNALS FOR HIGH PERFORMANCE DATA TRANSFER, Ser. No. 08/326,190;
LOW LATENCY ERROR REPORTING FOR HIGH PERFORMANCE BUS, Ser. No. 08/326,203.
Each of such cross-referenced applications are hereby incorporated by reference into this Application as though fully set forth herein.
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to data processing systems and, in particular, to a system and method for intelligent communication of bus requests and bus grants within a data processing system.
BACKGROUND OF THE INVENTION
Conventional data processing systems, especially multiprocessor systems, allocate access to the shared system bus coupling the various bus devices to system memory through a mechanism whereby individual bus devices each control access to the system bus. Typically, each bus device will queue it's individual bus requests for various operations internally. Then, each bus device makes the determination of which of the various operations it wishes to perform on the system bus by sending the appropriate corresponding bus request to the system controller. Thus, each individual bus device determines internally which of its bus request has higher priority. The system controller is then required to arbitrate between the received bus requests from the individual bus devices.
One disadvantage of this arbitration mechanism is that a portion of the decision process for accessing the various resources coupled to the system bus is delegated to each of the bus devices. As a results, the system controller is only able to view a portion of all of the various requests from the individual bus devices, since each of the individual bus devices retains and queues a significant number of bus request. Thus, there is a need in the art for a more efficient arbitration mechanism for granting access to the system bus.
SUMMARY OF THE INVENTION
It is an object of the present invention to centralize the decision-making process for granting access to the system bus. In an attainment of this object, the present invention provides a mechanism of transferring all of the queued bus requests from the individual bus devices to the system controller, which has a centralized knowledge of the availability of all of the system resources coupled to the system bus.
The system controller samples the bus devices' requests on a cycle-by-cycle basis. The requests are encoded, which allows each of the bus devices to precisely communicate to the system controller each of their internally “queued” operations. Quickly transferring these “descriptive and pipelined” bus requests from each of the bus devices to a centralized control point, allows the system controller to “optimize” the system bus utilization by prioritizing all of the requested bus operations and pipelining the appropriate bus grants.
One advantage of the present invention is that it provides an ability to transfer “intelligent” bus request information from each bus device to the system controller, and provides the ability to transfer multiple packets of bus requests information (via encoding and serialization techniques).
Another advantage of the present invention is that the bus requests are compact and can be issued in a pipelined manner and that bus grants may be pipelined to either the same bus device or different bus devices.
Yet another advantage of the present invention is that it supports latch-to-latch or non-latch-to-latch implementations. Those skilled in the art will appreciate the benefit of accommodating both implementations. (Latch-to-latch implementations allow higher system bus clocks rates, while non-latch-to-latch implementations provides lower system bus latencies.)
Yet still another advantage of the present invention is that the queuing of descriptive bus requests allows the system controller to efficiently control, distribute, and allocate system bus resources.
And, yet still another advantage of the present invention is that the system controller may resolve system level multiprocessor problems such as deadlocks and livelocks. Unlike traditional arbitration techniques, the present invention bus does not require bus devices to adhere to any arbitration “fairness” protocols.
Another advantages of the present invention is that the bus devices may support speculative bus requests and the system controller may support speculative bus grants.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
REFERENCES:
patent: 4482949 (1984-11-01), Gates
patent: 4924380 (1990-05-01), McKinney et al.
patent: 4953081 (1990-08-01), Feal et al.
patent: 5006982 (1991-04-01), Ebersole et al.
patent: 5050066 (1991-09-01), Myers et al.
patent: 5103393 (1992-04-01), Harris et al.
patent: 5202966 (1993-04-01), Woodson
patent: 5303382 (1994-04-01), Buch et al.
patent: 5335335 (1994-08-01), Jackson et al.
patent: 5416910 (1995-05-01), Moyer et al.
patent: 5426765 (1995-06-01), Stevens et al.
patent: 5442634 (1995-08-01), Cizek
patent: 5448701 (1995-09-01), Metz, Jr. et al.
patent: 5473762 (1995-12-01), Krein et al.
patent: 5485586 (1996-01-01), Brash et al.
patent: 5506995 (1996-04-01), Yoshimoto et al.
patent: 5623628 (1997-04-01), Brayton et al.
patent: 0 488 771 A2 (1992-06-01), None
patent: 4-116762 (1972-04-01), None
patent: 1-305461 (1989-12-01), None
patent: 2-79153 (1990-03-01), None
patent: 2-222058 (1990-09-01), None
patent: 4-311250 (1992-11-01), None
patent: 5-210640 (1993-08-01), None
patent: 5-313923 (1993-11-01), None
patent: WO 91/20041 (1991-12-01), None
Arimilli Ravi Kumar
Kaiser John Michael
England Anthony V. S.
Etienne Ario
International Business Machines - Corporation
Kordzik Kelly K.
Winstead Sechrest & Minick P.C.
LandOfFree
Queued arbitration mechanism for data processing system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Queued arbitration mechanism for data processing system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Queued arbitration mechanism for data processing system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2519242