Queued arbitration mechanism for data processing system

Details Queued arbitration mechanism for data processing system Queued arbitration mechanism for data processing system

1994-10-03

2000-02-22

Auve, Glenn A.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710113, 710116, G06F 1320

Patent

active

060292172

ABSTRACT:
A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus utilization via prioritization of all of the requested bus operations and pipelining appropriate bus grants. Intelligent bus request information is transferred to the system controller via encoding and serialization techniques.

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