Queue ordering for memory and I/O transactions in a multiple con

Details Queue ordering for memory and I/O transactions in a multiple con Queue ordering for memory and I/O transactions in a multiple con

1996-12-16

1999-05-18

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395287, 395309, 395310, 711117, 711118, 711141, 711142, 711143, 711146, G06F13/14

Patent

active

059058765

ABSTRACT:
A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the computing system, and facilitates concurrence of the transactions so as to enable high-bandwidth, deadlock-free operation. I/O to memory transactions and processor to memory transactions are placed in a memory request queue in the order in which such transactions appear on the processor bus; I/O to memory transactions are placed in an inbound request queue in the order such transactions appear on the I/O bus; and processor to I/O transactions and completions corresponding to split-transaction I/O to memory read transactions are placed in an outbound request queue in the order in which the split-transaction I/O to memory read transactions and the processor to I/O transactions appear on the processor bus.

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