Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-10-19
2008-11-11
Kim, Matt (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C710S018000
Reexamination Certificate
active
07451272
ABSTRACT:
A method and system of organizing a cache memory system based on a temporal-access pattern is disclosed. One or more data entries may be stored in a memory. One or more cache entries of the one or more data entries may be stored in a temporal cache. The one or more cache entries may be physically organized based on a temporal access pattern. A cache entry of the one or more cache entries may be based upon a condition.
REFERENCES:
patent: 6131144 (2000-10-01), Koppala
patent: 6237065 (2001-05-01), Banerjia et al.
patent: 2003/0088739 (2003-05-01), Wilkes et al.
patent: 1 011 049 (2000-06-01), None
patent: 1011049 (2000-06-01), None
Hilton Ronald N.
Penacho Victor
Woffinden Gary A.
Dudek Edward J
Kenyon & Kenyon
Kim Matt
Platform Solutions Incorporated
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