Queue management system having one read and one write per...

Details Queue management system having one read and one write per... Queue management system having one read and one write per...

1999-10-27

2004-06-22

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S052000, C710S054000, C370S232000, C370S389000, C370S398000, C370S412000, C370S418000, C370S429000

Reexamination Certificate

active

06754742

ABSTRACT:

FIELD OF INVENTION
The present invention relates to a buffer memory, a method and a buffer controller for queue management, and more particularly, to a buffer memory usable in an ATM switch and having only one read and one write port.
BACKGROUND OF THE INVENTION
It is generally desirable to achieve a high frequency throughput of data cells in a buffer memory. However, for reasons of keeping the complexity of such a memory moderate, it is desirable to limit the number of ports of the memory. A memory with only one read port and one write port allows one read operation and one write operation per cycle which implies that the memory itself is required to operate at a high frequency in order to manage the high bandwidth. This requires the buffer memory to be pipelined.
An object of the present invention is to enable a high frequency output in a pipelined buffer memory with only one read and write per cycle, by means of free-queues and a tailored queue management algorithm. The relation between the pipelining of the memory and the number of free queues is such that there is one additional free-queue per pipeline stage in the buffer. This object is achieved by means of a buffer memory, a method for queue management and a buffer controller.
SUMMARY OF THE DISCLOSURE
The above object is achieved by means of a buffer memory, a method for queue management and a buffer controller as claimed in claims
1
,
7
and
10
, respectively.
Using high operating frequencies means that it is necessary to pipeline the reading. In a preferred embodiment of the invention this pipelining is enabled by using two free-queues, that is one queue is working while the other is updated.


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