Quaternary FET read only memory

Details Quaternary FET read only memory Quaternary FET read only memory

1981-02-27

1987-04-14

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365184, 365178, 365 45, 365168, 357 2312, G11C 1140

Patent

active

RE0324019

ABSTRACT:
A quaternary FET read only memory is disclosed wherein each FET storage element in the array has its threshold adjusted by ion-implantation to one of four values. Each FET element in the array has its drain connected to a drain potential V.sub.DD. A binary input signal from a conventional binary, true/complement generator will then enable the gate of a selected FET storage cell and the output potential at the source of that selected storage cell will be V.sub.DD minus the customized threshold voltage of that storage cell, which is output at an output node. The signal on the output node is a quaternary signal which may be amplified by a quaternary sense amplifier circuit and then converted from quaternary to binary signal by means of a converter. The quaternary read only memory is capable of storing twice as much information per unit area as is a conventional FET binary read only memory. The concept may be expanded to N levels of information storage, using FET array devices with N different threshold voltages.

REFERENCES:
patent: 3623023 (1971-11-01), Olekstak
patent: 3909806 (1975-09-01), Uchida
patent: 4054864 (1977-10-01), Audaire
patent: 4142176 (1979-02-01), Dozier
patent: 4192014 (1980-03-01), Claycraft
patent: 4272830 (1981-06-01), Moench
IBM TDB, Oct. 1974, p. 1356, "Multiple Threshold IGFET Ternary Circuits by A. H. Dansky, vol. 17, No. 5.

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