Quasi-vertical LDMOS device having closed cell layout

Details Quasi-vertical LDMOS device having closed cell layout Quasi-vertical LDMOS device having closed cell layout

2006-03-14

2008-11-04

Nguyen, Kimberly D (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S327000, C257S335000, C257S344000, C257S408000

Reexamination Certificate

active

07446375

ABSTRACT:
A low voltage power device includes a plurality of quasi-vertical LDMOS device cells. A conductive trench sinker is formed through the epitaxial layer and adjacent a selected one of the source and drain regions in each cell. The trench sinker electrically couples the selected one of the source and drain regions to the substrate for coupling current from the channel to the substrate. The resulting device exhibits a vertical current flow between the metal electrode covering the front surface and the second electrode formed at the back side of the wafer. The device cells are arranged in a closed cell configuration.

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