Quasi-differential read operation

Details Quasi-differential read operation Quasi-differential read operation

2007-06-29

2009-08-04

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Systems using particular element

Resistive

C365S203000, C365S189011, C365S189040, C365S207000

Reexamination Certificate

active

07570507

ABSTRACT:
A memory device includes an array portion of resistive memory cells comprising a plurality of bit line pairs. The device further includes a read circuit operably associated with a first charged line, wherein the read circuit comprises a precharge circuit configured to charge a first line at a first rate, and to charge a second line at a second rate, the first and second charge rates based on a state of a memory cell coupled between the respective lines. The read circuit may further include a ground circuit configured to pull the respective lines to a ground potential, and a sense circuit coupled to the line pair configured to sense a differential voltage between the line pair in response to the state of the memory cell.

REFERENCES:
patent: 6985389 (2006-01-01), Ma
patent: 2004/0225829 (2004-11-01), Akiyama et al.
patent: 2006/0146634 (2006-07-01), Osada et al.
patent: 2007/0147102 (2007-06-01), Roehr

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