Quasi-complementary BiCMOS circuit with enhanced pull down trans

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Bipolar and fet

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326 27, H03K 19082, H03K 1716

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active

058865420

ABSTRACT:
A quasi-complementary BICMOS circuit (46) having a clamp circuit that automatically discharges the base-collector of a pull down bipolar transistor (16) when the transistor's (16) collector voltage equalizes its base voltage. The action is immediate and does not depend on the performance of a feedback circuit to provide the timing of the arrival of the clamp signal. The clamp circuit reduces the amount of shallow saturation and quickly discharges shallow saturation after the pull down transition. The degree of shallow saturation is controllable by size selection of the clamp transistor (48). The clamp circuit also discharges the transistor's (16) base voltage to ground potential.

REFERENCES:
patent: 4649294 (1987-03-01), McLaughlin
patent: 4719373 (1988-01-01), Masuda
patent: 4829201 (1989-05-01), Masuda
patent: 4970414 (1990-11-01), Ruth, Jr.
patent: 5057713 (1991-10-01), Iwamura
patent: 5111077 (1992-05-01), Young
patent: 5182472 (1993-01-01), Ando
Yano, et al. "Quasi-Complementary BiCMOS for Sub-3-V Digital Circuits", IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991, pp. 1708-1718.

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