Quantum thin line producing method and semiconductor device

Details Quantum thin line producing method and semiconductor device Quantum thin line producing method and semiconductor device

2000-01-28

2002-02-12

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S585000, C438S607000, C438S962000

Reexamination Certificate

active

06346436

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a quantum thin line producing method for forming a quantum thin line constructed of a metal or semiconductor that is minute enough to cause a quantum size effect on an insulating substrate or a semiconductor substrate via an insulating layer and to a semiconductor device employing this quantum thin line.
The large-scale integrated circuits (LSIs) that have supported the development of electronics and currently become the industrial nucleus have made great strides in terms of their performances toward larger capacity, higher speed, lower consumption of power and so on through the microstructural progress thereof. However, it is considered that the conventional device reaches the limit in terms of the principle of operation when the device size becomes 0.1 &mgr;m or smaller, and accordingly, there are conducted energetic researches on a new device based on a new principle of operation. As for this new device, there is a device having a microstructure called the nanometer-size quantum dot or quantum thin line. The nanometer-size quantum dot is energetically examined together with a variety of quantum effect devices, particularly for the application thereof to a single electron device utilizing the Coulomb blockade phenomenon. The nanometer-size quantum thin line is expected to be applied to a super high-speed transistor utilizing the quantum effect.
Particularly, in regard to the nanometer-size quantum thin line, there is carried out trial production of a semiconductor quantum device based on a new principle of operation that the degree of freedom of an electron is limited by confining the electron in a semiconductor layer having a width approximately equal to that of the electron wavelength (de Broglie wavelength) in a semiconductor crystal and a quantization phenomenon caused by this is utilized. That is, the wavelength of an electron in a semiconductor layer is about 10 nm. Therefore, it is theoretically derived that, if an electron is confined in a semiconductor thin line (quantum thin line) having a width of about 10 nm, then the electron can move in this thin line while being scarcely deviated, for the achievement of the increased mobility of the electron.
Therefore, by forming a conductive layer in which a number of quantum thin lines as described above are arranged in a plane and controlling the number of electrons inside this conductive layer by the operation of a gate electrode, there can be produced a quantum thin line transistor having a higher operating speed than the conventional transistor. By incorporating a number of quantum thin lines as described above into a laser light emitting layer, there can be obtained a high-efficiency semiconductor laser device that has a sharp spectrum and excellent high-frequency characteristics even with a small injection current.
Conventionally, as a method for forming the aforementioned quantum thin line, there have been proposed methods as disclosed in the following reference documents (1) through (3).
(1) Ishiguro, et al., Japan Society of Applied Physics, spring in 1996, Lecture No. 28a-PB-5, proceeding p-798 and Lecture No. 26p-ZA-12, proceeding p-64
FIGS. 15A through 15D
are process charts showing the “Method for uniformly producing Si quantum thin line on a SIMOX (separation by implanted oxygen) substrate utilizing anisotropic etching” disclosed in the above reference document (1).
Referring to
FIGS. 15A through 15D
, first, as shown in
FIG. 15A
, silicon nitride (Si
3
N
4
) is deposited on a (100)-SIMOX substrate constructed of a silicon substrate
1
, an oxide film
2
and a SOI (silicon-on insulator) film
3
, and thereafter patterning is performed to form a silicon nitride film
4
. Next, as shown in
FIG. 15B
, anisotropic etching is performed with TMAH (tetramethylammonium hydroxide) using the silicon nitride film
4
as a mask, consequently forming a. SOI film
5
having a (111) plane on a pattern edge.
Next, as shown in
FIG. 15C
, the (111) plane of the side wall of the SOI film
5
is selectively oxidized using the silicon nitride film
4
as a mask, consequently forming an oxide film
6
. Then, as shown in
FIG. 15D
, the silicon nitride film
4
is removed, and thereafter anisotropic etching is performed again with TMAH using the oxide film
6
as a mask, consequently forming a Si quantum thin line
7
.
The width of this Si quantum thin line
7
is determined depending on the film thickness of the SOI film
3
, and practically a thin line of about 10 nm is formed. In a quantum thin line MOSFET (metal-oxide-semiconductor field-effect transistor) formed by employing the thus-formed Si quantum thin line
7
as a channel region, there is observed Coulomb blockade vibration that is the characteristic of the quantization phenomenon.
(2) Japanese Patent Laid-Open Publication No. HEI 6-77180
FIGS. 16A through 16C
are process charts showing the “quantum thin line forming method utilizing thin-line-shaped etching mask by side wall method” disclosed in the above reference document (2).
Referring to
FIGS. 16A through 16C
, first, as shown in
FIG. 16A
, a resist
12
is formed by patterning on a substrate
11
of GaAs to be etched, and a SiO
2
film
13
having a film thickness of 50 nm is further formed on them by plasma-activated chemical vapor deposition (PCVD). Next, as shown in
FIG. 16B
, reactive ion etching is performed to form a side wall
14
of SiO
2
on both side walls of the patterned resist
12
.
Finally, as shown in
FIG. 16C
, the resist
12
is removed, and thereafter the substrate
11
of GaAs to be etched is patterned by reactive ion etching using the SiO
2
side wall
14
as a mask, consequently forming a thin line made of GaAs.
(3) Japanese Patent Laid-Open Publication No. HEI 8-288499
FIGS. 17A through 17G
are process charts showing the “quantum thin line forming method utilizing sticking of two Si wafers and etching mask of wall formation” disclosed in the above reference document (3).
Referring to
FIGS. 17A through 17G
, first, as shown in
FIG. 17A
, a protruding portion
22
is formed on a Si substrate
21
by dry etching. Subsequently, as shown in
FIG. 17B
, a SiOx-based insulating film
23
is formed so as to flatten the entire substrate. Next, as shown in
FIG. 17C
, the flattened substrate is entirely inverted and stuck on another Si substrate
24
with the SiOx-based insulating film
23
side put in contact with the substrate
24
. Next, as shown in
FIG. 17D
, the Si substrate
21
is abraded by the CMP (chemical-mechanical polishing) method until the SiOx-based insulating film
23
is exposed. As a result, an island-shaped Si layer
25
of a thickness of about 10 nm is left as buried in the SiOx-based insulating film
23
. Then, by forming a polysilicon layer including an impurity to a thickness of about 10 nm by the thermal CVD (chemical vapor deposition) method and thereafter performing anisotropic etching via a resist mask (not shown), there is formed a polysilicon pattern
26
where the processed end surface is positioned in the vicinity of the center of the island-shaped Si layer
25
.
Next, as shown in
FIG. 17E
, a thermo-oxidized film (SiOx)
27
having a film thickness of 1 nm to 10 nm is formed on the Si exposed portions
25
and
26
through a thermo-oxidizing process. Next, as shown in
FIG. 17F
, by etching back performed, a side wall
28
is formed with the thermo-oxidized film
27
left on the processed end surface of the polysilicon pattern
26
. Next, as shown in
FIG. 17G
, the island-shaped Si layer
25
is subjected to wet processing on condition that a selection ratio relative to the island-shaped layer
25
can be assured, consequently removing the polysilicon pattern
26
. Subsequently, the island-shaped Si layer
25
is etched on condition that the selection ratio relative to SiOx that forms the side wall
28
can be assured, consequently forming a quantum thin line
29
.
However, the conventional quantum thin line forming methods disclosed in the aforementioned reference documents (1) through (3) hav

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