Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-02-10
2002-02-26
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S317000, C257S318000, C257S319000, C257S320000, C257S014000, 43, 43, 43, 43, 43
Reexamination Certificate
active
06351007
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for producing a minute particle or a quantum thin line constructed of a metal or semiconductor that is minute enough to cause a quantum size effect on an insulating substrate or a semiconductor substrate via an insulating layer and to a semiconductor device that employs a quantum thin line utilized as a single electron device or a quantum effect device.
The large-scale integrated circuits (LSIs) that have supported the development of electronics and currently become the industrial nucleus have made great strides in terms of their performances toward larger capacity, higher speed, lower consumption of power and so on through the microstructural progress thereof. However, it is considered that the conventional device reaches the limit in terms of the principle of operation when the device size becomes 0.1 &mgr;m or smaller, and accordingly, there are conducted energetic researches on a new device based on a new principle of operation. As to this new device, there is a device having a microstructure called the nanometer-size quantum dot or quantum thin line. The nanometer-size quantum dot is energetically examined together with a variety of quantum effect devices, particularly for the application thereof to a single electron device utilizing the Coulomb blockade phenomenon. The nanometer-size quantum thin line is expected to be applied to a super-high-speed transistor utilizing the quantum effect.
Particularly, in regard to the quantum thin line, there is carried out trial production of a semiconductor quantum device based on a new principle of operation that the degree of freedom of an electron is limited by confining the electron in a semiconductor layer having a width approximately equal to that of the electron wavelength (de Broglie wavelength) in a semiconductor crystal and a quantization phenomenon caused by this is utilized. The wavelength of an electron in a semiconductor layer is about 10 nm. Therefore, it is theoretically derived that, if an electron is confined in a semiconductor thin line (quantum thin line) having a width of about 10 nm, then the electron can move in this thin line while being scarcely scattered, for the achievement of the increased mobility of the electron. By forming a conductive layer in which a number of quantum thin lines as described above are arranged in a plane and controlling the number of electrons inside this layer by the operation of a gate electrode, there can be produced a quantum thin line transistor having a higher operating speed than that of the conventional transistor. By incorporating a number of the above quantum thin lines into a laser light emitting layer, there can be obtained a semiconductor laser device that has a sharp spectrum, high-efficiency and excellent high-frequency characteristics even with a small injection current.
Conventionally, as a method for forming a quantum thin line, there have been proposed methods as disclosed in the following reference documents (1) and (2).
(1) Japanese Patent Laid-Open Publication No. HEI 5-29632
FIGS. 15A through 15F
are process charts showing the “Method for producing silicon quantum thin line on silicon substrate utilizing anisotropic etching” disclosed in the above reference document (1).
First, as shown in
FIG. 15A
, an etching mask
112
made from a silicon oxide film or a silicon nitride film is formed on a silicon (
100
)-substrate
111
. Next, as shown in
FIG. 15B
, the silicon (
100
)-substrate is etched by using a silicon anisotropic etching liquid of potassium hydroxide water and so on having an etching rate characteristic that largely varies depending on the orientation of silicon. Since the etching rate of the (
111
) plane is slower than the etching rate of the (
110
) plane and (
100
) plane by about two orders of magnitude, a projecting portion having a triangular cross-section shape is formed on the surface of the silicon (
100
)-substrate
111
after etching.
Next, as shown in
FIG. 15C
, after the removal of the etching mask
112
(shown in FIG.
15
B), a silicon nitride film
113
that becomes an oxidation-resistant mask layer is formed, and thereafter a resist pattern
114
is formed so as to cover at least the top of the projecting portion having a triangular cross-section shape.
Next, as shown in
FIG. 15D
, the silicon nitride film
113
is etched using a resist
114
as a mask, and further the silicon (
100
)-substrate
111
is subjected to isotropic etching.
Next, as shown in
FIG. 15E
, after the removal of the resist
114
(shown in FIG.
15
D), the silicon (
100
)-substrate
111
is oxidized to form an oxide film
116
. In this stage, the silicon nitride film
113
serves as the oxidation-resistant mask, and therefore, a portion in the vicinity (indicated by the reference numeral
115
in
FIG. 15E
) of the top of the projecting portion having a triangular cross-section shape is not oxidized.
Finally, as shown in
FIG. 15F
, if the silicon nitride film
113
(shown in
FIG. 15E
) is removed, then a silicon thin line
115
that is insulated and isolated from the silicon (
100
)-substrate
111
by the oxide film
116
is formed at the top of the projecting portion having a triangular cross-section shape.
(2) Japanese Patent Laid-Open Publication No. HEI 8-288499
FIGS. 16A through 16G
are process charts showing the “Quantum thin line forming method utilizing sticking of two silicon wafers and etching mask composed of aside wall” disclosed in the above reference document (2).
First, as shown in
FIG. 16A
, a projecting portion
122
having a thickness of about 10 nm is formed on a silicon substrate
121
by dry etching.
Subsequently, as shown in
FIG. 16B
, a SiOx-based insulating film
123
is formed so as to flatten the entire substrate.
Next, as shown in
FIG. 16C
, the substrate is inverted from the state shown in FIG.
16
B and stuck on another silicon substrate
124
with the surface of the SiOx-based insulating film
123
put in contact with the silicon substrate
124
.
Next, as shown in
FIG. 16D
, the silicon substrate
121
(shown in
FIG. 16C
) is abraded by the CMP (Chemical Mechanical Polishing) method until the SiOx-based insulating film
123
is exposed. In this case, an island-shaped silicon layer
125
is left as buried in the SiOx-based insulating film
123
.
Next, by forming a polysilicon layer including an impurity to a thickness of about 10 nm by the thermal CVD (Chemical Vapor Deposition) method and thereafter performing anisotropic etching via a resist mask, there is formed a polysilicon pattern
126
where the processed end surface is positioned in the vicinity of the center of the island-shaped silicon layer
125
.
Next, as shown in
FIG. 16E
, a thermo-oxidized film
127
having a film thickness of 1 to 10 nm is formed on the exposed portion of the island-shaped silicon layer
125
and the polysilicon pattern
126
through a thermo-oxidizing process.
Next, as shown in
FIG. 16F
, a side wall
128
is formed on the processed end surface of the polysilicon pattern
126
by etchback.
Next, as shown in
FIG. 16G
, wet processing is performed on condition that a selection ratio relative to the island-shaped silicon
125
can be assured, consequently removing the polysilicon pattern
126
(shown in FIG.
16
F). Subsequently, the island-shaped silicon
125
(shown in
FIG. 16F
) is etched on condition that the selection ratio relative to a SiOx side wall
128
can be assured, consequently forming a quantum thin line
129
.
The aforementioned prior art techniques (1) and (2) have the problems as follows.
(1) According to the “Method for producing silicon quantum thin line on silicon substrate utilizing anisotropic etching” of the aforementioned reference document of Japanese Patent Laid-Open Publication No. HEI 5-29632, the silicon thin line is formed at the top of the silicon substrate having a triangular cross-section shape. Therefore, the surface flatness of the silicon substrate becomes degraded as a consequence of an increase in size of the stepped portion on the
Ashida Tsutomu
Fukushima Yasumori
Kang Donghee
Loke Steven
Nixon & Vanderhye P.C.
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