Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-11
2003-05-27
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06570224
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of electronic components and conductors, and, in particular to multifuctional and electronic components of integrated circuits (ICs) having minimum accessible outline dimensions, maximum speed and maximum operating temperature. The components and conductors working on basis of quantum size resonance effects are used for constructing two-dimensional (planar) and three-dimensional electronic devices, ICs designed for processing and converting of analog and digital information, as well as for transmitting electric signals and energy loss-free.
BACKGROUND OF THE INVENTION
IC elements tend to scale down. However at downsizing of IC elements to less than 100 nm, charge carriers start revealing the discreet nature and the quantum mechanical characteristics thereof, what makes influence on constructive features of active devices, i.e. transistors.
At the same time, at the dimension of less than 100 nm separate transistor elements, actually are small particles, i.e. clusters [1]. Downsizing a cluster may create a condition allowing to design devices that are able to control groups of electrons, and even one electron.
Prior art describes a large class of electronic devices basing on single-electron tunnelling through a small size cluster [2]. The simplest variant of such a device is a kind of analogue of a field-effect semiconductor transistor comprising between the drain and the source thereof an isolator with a built-in small cluster in the centre. Such a transistor is generally referred as SET—Electron Transistor).
A cluster built-in the isolator of a SET device has its own capacity in relation to the substrate C
c
. The core of the effect disclosed in [2] is that during tunnel passage through the cluster of an electron with e-charge, the electron changes the potential of the cluster by the magnitude &Dgr;U=e/C
c
and blocks by its field the passage of other electrons for a while it is present at the cluster. In the process, it is necessary that the potential at the cluster exceeded the potential of the thermal noises of the cluster capacitance:
&Dgr;
U≧
2
kT/e
(I)
wherein k is the Boltzmann's constant, T is an absolute temperature.
For example a spherical silicon cluster with a radius r
c
=5 nm having a dielectric permeability ∈=11.7, will have the capacitance C
c
=4&pgr;∈
0
∈r
c
and, hence on basis of (1) will have the maximum operating temperature of the device
T=e
2
/(8&pgr;∈
0
∈r
c
k
)=143 K(−130° C.) (2)
wherein ∈
0
is the vacuum dielectric constant.
This condition shows that use of materials with ∈<5.6 or clusters of the smaller size, generally provides a possibility of designing a single-electronic quantum device, operable at the normal temperature—290-300 K (17-27° C.). However, there is no physical sense in considering a separate cluster as a microcircuit component without taking into consideration the capacitance of transistor electrodes. Therefore there exists a problem of considering all parasitic capacitances.
As it is disclosed in [3] a field semiconductor transistor with the isolated gate may register a single electron. In this case the structure of the proper transistor canal does not influence the analysis. Therefore for any devices of this kind, including nanometer devices, it is necessary to consider the input capacitance C
i
as well as the output capacitance C
a
. Thus, the multiplier C
a
/C
i
, should be added to the formula (1) in accordance with [3, formula (7.36)]
(
C
a
/C
i
)·(
e/C
c
)≧2
kT/e
(3)
From this expression follows that, in case the entrance control signal is present on the gate or cluster and the conductor has an admissible size, e.g. the conductor length is about ~1000 nm and the conductor width is about ~10 nm, the conductor capacitance for a silicon substrate will be C
i
≈100C
c
. Accordingly, at the acceptable speed the operating temperature of the device is in all T=1.43° K (−271.72° C.). Right this temperature is the limit for the most of known SET-devices [4-7]. The said researches, which describe approaches to realising high temperature single electronic tunnelling, in fact made use of one and the same method disclosed in [2]. For example, metal clusters of a size less than 50 nm were placed between two electrodes applied to a dielectric [4] or similarly, fullerene clusters of a size at all 0.634 nm were regularly spaced in the dielectric layer [5]. Various logical devices for designing the digital memory with logical elements having a size of structures from 0.2 nm to 100 nm are investigated in [6,7]. Meanwhile, the paper [2], being a close prior art solution for all the aforementioned papers, has got a mistake of principle. In particular, the dimensionless coefficient C
a
/C
i
was not considered in the paper [2]. As a result, the mistake from the paper [2] propagated to the majority of patents, in which the single tunneling principle was used. Due to this error a large number of patents granted for SET devices are to be transferred to the category of pure scientific papers having no commercial use. Meanwhile, it is very difficult to rectify this error by technical methods, whereas all active elements should be connected by electric conductors, the size of which could hardly be diminished to the size of the most active element. Hence, a big parasitic capacitance of supply electrodes will always exist. In fact, the only known solution of this problem exhibit biological objects. For example, in the brain of an animal information is transferred between the active elements—neurons—not by means of passive electric conductors, but rather by means of specific conductors—axons. Practically, axons are active distributed communication lines, i.e. axons consume external energy for creating a process of transferring electric impulse. If neuron-axon links are considered as the most close prior art, then the problems will be created by their big sizes (of the order of micrometers) and slow advance of electric impulses (several meters per second) caused by the ion-type conductivity. For the rest, this principle may serve for the present invention as a good prior art solution. Moreover, brain is a distributed computing system (of a neuron type) relating to self-learning systems. Hence, brain elements—neurons—may serve as prior art logical elements for the claimed invention.
In a number of other researches [8] the more traditional methods make use of building-in a cluster in a gate insulator of a field transistor. Charging and discharging the said cluster yet by a group of electrons tunnelling through the dielectric (insulator) provides a possibility to change the characteristics of the field transistor so that to create an analog or digital memory. However, the time of charge storage is insufficient in this case.
It is obvious from the descriptions of the aforementioned patents that space capacitances of conductors that connect transistors were not considered there. And naturally, operating temperatures exceeding the temperature of fluid helium were not obtained there.
The research [9] corresponds to a certain progress in the field of increasing operating temperatures of SET devices to normal conditions. The authors placed a 30-nm titan cluster between titanium electrodes of the 3-nm thickness spaced at a distance of 50 nm. The gap between the cluster and electrodes was filled with tunnel-transparent dielectric of TiO
x
. Supplying at normal temperature a small voltage of 0.1-0.7 V produces four N-shape regions in voltage-current characteristics. This extraordinary effect was explained by a single electron tunnelling. Meanwhile, being aware that the titanium oxide has ∈=24 and taking additionally into consideration capacitance of the cluster and electrodes respective the substrate it is o
David Newman Chrtd.
Prenty Mark V.
LandOfFree
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