Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-07
2003-11-18
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000
Reexamination Certificate
active
06649966
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating thereof, and more particularly, to a single electron semiconductor device and method thereof.
2. Background of the Related Art
In response to the semiconductor industry's desire to further integrate semiconductor devices, a single electron memory device has been developed which is programmable and erasable by using just a single or a few electrons.
FIG. 1
shows a structure of a single electron memory device in accordance with the related art where a semiconductor layer
100
made of silicon or gallium-arsenic (GaAs) is formed with a tunneling insulation film
102
on the upper surface of the semiconductor layer
100
. The tunneling insulation film
102
is formed by a silicon oxide film having a thickness of 2-3 nm. Next, a quantum dot
104
is formed on the upper surface of the tunneling insulation film
102
of a fine-sized polycrystalline silicon pattern having a width of about 50 nm and a height of about 50 nm. The size of the quantum dot
104
is preferably such that a single electron or several electrons at the most can tunnel to generate a Coulomb Blockade phenomenon.
A control insulation film
106
is formed on the upper surface of the quantum dot
104
. The control insulation film
106
is a silicon oxide film or a silicon nitride film formed with a thickness of about 2-3 nm. Next, a control gate electrode
108
is formed on the upper surface of the control insulation film
106
.
An n-type or a p-type of impurity ion-implanted source region
110
and a drain region
112
are formed in the semiconductor layer
100
at the both sides of the control gate electrode
108
. Then, an interlayer insulation film
114
is formed at the upper surface and side surface of the control gate electrode
108
, and a planarization layer
116
is formed on the upper surface of the interlayer insulation film
114
. A contact hole
117
is then formed on the upper surface of the source region
110
and the drain region
112
and a conductive plug
118
is formed through the contact hole
117
, where the conductive plug is connected with a metal wiring layer
120
.
The operational principle of a single electron memory having the construction of
FIG. 1
is the same as that of an EEPROM (Electrically Erasable Programmable Read Only Memory) of the related art. But, unlike an EEPROM of the related art, the single electron memory can vary a threshold voltage with merely single electron or several electrons at the most and is operable at a lower voltage than a EEPROM of the related art because when a write voltage higher than the threshold voltage is applied to the control gate electrode, an inversion layer is formed in a channel region and an electron from the source region is induced into the channel, reducing the channel conductance.
This occurs because one or several electrons when in the inversion layer of the channel region, tunnel into the quantum dot (which becomes a floating gate) and one by one the electrons tunnel through a thin tunneling insulation layer at room temperature. As the electrons tunnel into the floating quantum dot, the threshold voltage changes.
Ideally, it is preferred that a single electron tunnels for programming. However, since it is difficult to detect the change in the size of the threshold voltage, three or four electrons are often used to change the threshold voltage by about 1V to program the memory.
FIGS. 2A through 2H
show a series of processes of the method for fabricating a single electron memory device in accordance with the related art.
As shown in
FIG. 2A
, a plurality of device isolation regions
201
are formed at predetermined portions of a semiconductor layer
200
. The device isolation regions
201
are called field regions and the other regions which are not the device isolation regions
201
are called active regions. Next, a tunneling insulation layer
202
is formed on an upper surface of the semiconductor layer
200
including the field region
201
, then a polysilicon layer
203
is formed on the upper surface of the tunneling insulation layer
202
.
As shown in
FIGS. 2B and 2C
, the polysilicon layer
203
is patterned to form a polysilicon layer pattern
203
a
, the surface of the polysilicon layer pattern
203
a
is oxidized to form a silicon oxide film
204
on the surface of the polysilicon layer pattern
203
a
as illustrated in FIG.
2
C. Thereafter, as shown in
FIG. 2D
, the silicon oxide film
204
is selectively etched using a buffered HF solution to reduce the polysilicon layer pattern
203
a
to a smaller size polysilicon layer pattern
203
B.
The processes of
FIGS. 2C and 2D
are repeatedly performed until, as shown in
FIG. 2E
, a quantum dot
203
c
is formed having a length that is at most 50 nm. Next, as shown in
FIG. 2F
, a control insulation film
205
is formed on the upper surface of the polysilicon layer pattern
203
c
, the tunneling insulation layer
202
and the isolation regions
201
, and then a polysilicon layer
206
is deposited on the upper surface of the control insulation film
205
.
Next, as shown in
FIG. 2G
, the polysilicon layer
206
and the control insulation film
205
are patterned to form a control gate electrode
206
a
, source
207
and drain regions
208
are then formed on both sides of the control gate electrode
206
a
by implanting an impurity ion into the semiconductor layer
200
, and an interlayer insulation film
209
is formed on the entire upper surface of the structure formed on the semiconductor layer
200
. Then, a planarization layer
210
is formed on the upper surface of the interlayer insulation film
209
, a contact hole is then formed on both the source
207
and drain regions
208
and each contact hole is filled with a conductive material to form a conductive plug
211
as shown in FIG.
2
H. Finally, a metal wiring layer
212
is formed on the upper surface of the conductive plug
211
, thereby completing the fabricating of a single electron dot memory device.
However, the above method for fabricating a single electron memory device has various problems. For example, a very fine pattern must formed to form the quantum dot, but the smallest line feature that can currently be formed by using the currently available photolithography processes are about 0.1 &mgr;m. Accordingly, it is difficult to fabricate a quantum dot having a size less than 50 nm by using the currently available photolithography and an etching process which starts with pattern line features of about 0.1 &mgr;m.
Further, as mentioned above in the related art method, a comparatively large polysilicon layer pattern is formed, and then the size of the polysilicon layer pattern is reduced by using iterations of oxidation and wet etching. Accordingly, this method has a problem with the evenness of the size of the quantum dot because of the inexactness of the oxidation and wet etching and a problem with the reproduction of the process because of the iterations of oxidation and wet etching required to reduce the size of the quantum dot.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a quantum dot having a more consistent size.
Another object of the present invention is to provide a quantum dot having an improved reproductiveness of the process.
A further object of the present invention is to provide a single electron memory device.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a method for fabricating a quantum dot including the steps of forming a first insulation layer on a semiconductor layer, forming a
Fleshner & Kim LLP
Hynix / Semiconductor Inc.
Lindsay Jr. Walter L.
Niebling John F.
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