Qualification test method and circuit for a non-volatile memory

Details Qualification test method and circuit for a non-volatile memory Qualification test method and circuit for a non-volatile memory

2001-08-30

2003-05-13

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S185010

Reexamination Certificate

active

06563752

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. no. 90118850, filed Aug. 2, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a test circuit and method for a non-volatile memory. More particularly, the present invention relates to a qualification test method and circuit for a non-volatile memory with a trapping layer.
2. Description of Related Art
The non-volatile memory, such as flash EEPROM, usually has the gate structure with a control gate and a floating gate. The control gate is used to receive the activating control voltage of the memory cell, and the floating gate is used to store charges. In this structure, since the floating gate is usually a conductive body made of polysilicon, when the memory cell is programmed, the injected electrons to the floating gate would be distributed uniformly in the floating gate. Therefore, this kind of memory cell with the floating gate structure can only have one bit for memory. Afterward, it is proposed that the dielectric layer is used to replace the floating gate structure of the memory cell. Electrons can be locally confined by using the dielectric layer to confine electrons, whereby two bits in one memory cell can be achieved. This increases the capacity for the memory cell.
FIG. 1
is a cross-section view, illustrating a structure of a non-volatile memory cell, have a trapping layer with two bits. In
FIG. 1
, the substrate includes doped regions serving as a source region
18
and a drain region
16
for a memory cell. A gate structure is formed over the substrate. The gate structure can have a structure of oxide
10

itride
12
/oxide
14
. The nitride layer
12
serving as a trapping layer is used to capture electrons. Here, the channel hot electron injection and the band-to-band hot electron injection, respectively, are used to program and erase the memory cell.
Since the trapping layer
12
is not a conductive body, when electrons are trapped inside, electrons are confined to a side of the source region or the drain region. That is, when programming voltage is applied on the gate and the drain region, and the source region is applied with a voltage of 0V, a large electric field would occur at edge of the gate electrode and drain region. The electrons are trapped in the trapping layer at edge of the drain region, and are confined at the local region. On the contrary, when programming voltage is applied on the gate and the source region, and the drain region is applied with a voltage of 0V, a large electric field would occur at edge of the gate electrode and source region. The electrons are trapped in the trapping layer at edge of the source region, and are confined at the local region. In this manner, the two bits of storage is achieved, as shown in
FIG. 1
for the locations bit
1
and the bit
2
.
TABLE 1
V
g
(V)
V
s
(V)
V
d
(V)
V
b
(V)
Programming
Bit 1
10
4
0
0
Bit 2
10
0
4
0
Erasing
Bit 1
−3
−5
Floating
0
Bit 2
−3
Floating
−5
0
Reading
Bit 1
2.75
0
1.6
0
Bit 2
2.75
1.6
0
0
The operation voltage sets for different actions are shown in table 1.
The threshold voltage Vt of this kind of memory cell can be increased after the electrons are injected into the insulating layer
12
(program state). However, after the memory cell passes the program/erase cycle (P/E cycle), the threshold voltage of the programming state would reduce as the retention time increases. The lowered threshold voltage would increase the leakage current, and even cause a failure of storing information in the memory cell. For example, for the usual situation that the state of “0” has a threshold voltage higher than a specified level, the state of “1” and state of “0” cannot be correctly distinguished due to the reduced threshold voltage. This means that the information stored in the memory cell cannot be correctly read out.
Thus, in order to assure the memory to work properly for a long period after the memory cell is fabricated and packaged, and then sent to the user. A test is necessary to be performed, so as to ensure that the product can still properly work without invalidity after a long period of retention time even if the threshold voltage is reduced.
SUMMARY OF THE INVENTION
The invention uses the physical phenomena for an insulating trapping layer in the non-volatile memory and provides an effective testing method associate with an apparatus. The invention is an accelerating test performed in a period of test time, and can judge whether or not the memory array can properly work in an expected lifetime.
The invention provides a qualification test method for a non-volatile memory. First, a relation curve between the programming voltage and the lifetime of the memory cell is determined. Then, a programming voltage with respect to the memory array within the expected lifetime is estimated. According to the relation curve, the accelerating test voltage and the test time period corresponding to the programming voltage operated in the expected lifetime are computed out. The test is performed for the test time period under the accelerating test voltage. All the memory cells of the memory array at the programmed state are tested to see if the memory cells still have the original programmed state after the test time period. If the programmed state of all the memory cells in the memory array remains, the memory array is judged to have the lifetime. If the programmed state of partial of the memory cells in the memory array does not remain, the memory array is judged to fail during its lifetime.
The invention further provides a qualification test circuit for a non-volatile memory, used to test a memory array, which includes multiple memory cells arranged in columns and rows. Each of the rows is connected to a word line driver, and each of the columns is connected to a bit line bias circuit. The qualification test circuit for a non-volatile memory includes a programming voltage testing control unit, coupled to the memory array, used to test the programming state for each memory cell.
By means of foregoing accelerating test method and circuit, the accelerating programming voltage is used to test all the memory cells with the expected testing time period. After the expected testing time period, the programming state for the memory cells is checked whether or not the programming state still remain. If it is, then the memory cells are qualified to be able to properly work under the actual programming voltage within the expected lifetime. The invention thereby achieves the objective for the qualification test.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5930169 (1999-07-01), Iwata et al.
patent: 6000843 (1999-12-01), Sawada
patent: 6339557 (2002-01-01), Kawaguchi et al.

Affiliated with

Also associated with

Rating

Qualification test method and circuit for a non-volatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Qualification test method and circuit for a non-volatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Qualification test method and circuit for a non-volatile memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3006324