Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-08-20
2003-12-23
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06668365
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to computer-aided design tools for generating IC layouts and in particular to a method for eliminating cell overlap and routing congestion in an IC layout.
2. Description of Related Art
FIG. 1
illustrates a typical integrated circuit (IC) design process flow. An IC designer usually begins the IC design process by producing a register transfer language (RTL) “netlist”
10
, a file describing the IC circuit as a set of nets (signal paths) interconnecting terminals of the various circuit devices (“cells”) to be included in the IC. In a high level RTL netlist cells may be described in terms of the logic they carry out, using Boolean expressions to define logical relationships between device input and output signals. After employing circuit simulation and verification tools
11
to check the logic of the IC described by RTL level netlist
10
, the designer uses a synthesis tool
12
to convert RTL level netlist
10
into a “gate level” netlist
14
describing each cell by referring to an entry for that cell in a cell library
13
, which includes an entry for each cell that may be incorporated into an IC design. Cells described by cell library
13
may range from very small devices such as individual transistors, to small components such as logic gate formed by several transistors, up to very large components such as computer processors and memories.
The cell library entry for each cell contains a model of the time-dependent behavior of the cell that can be used to represent the cell when a gate level netlist
14
incorporating the cell into an IC design is subjected to simulation and verification
11
. A simulation based on gate level netlist
14
more accurately predicts the behavior of the IC than a simulation based on RTL level netlist
10
. However since the gate level netlist
14
does not model the networks interconnecting the cells, the simulation and verification results at this stage of the design do not take into account signal path delays in the nets.
After verifying the behavior of the circuit described by gate level netlist
14
, the circuit designer employs computer-aided placement and routing (P&R) tools
16
to convert gate level netlist
14
into an IC layout describing how each cell is to be formed and positioned within a semiconductor substrate and describing how the nets interconnecting the cells are to be routed. The cell library entry for each cell also contains a detailed description of the cell's layout telling the P&R tools
16
how to lay out that cell. The P&R tools determine where to place each cell and how to orient each cell in the substrate and also determine how to route the nets that interconnect the cells.
As P&R tools
16
create an IC layout, a “netlist updater”
20
updates the gate level netlist
14
to produce a “layout level” netlist
22
not only models the cells forming the IC but also models the signal path delays within the nets interconnecting the cells. After P&R tools
16
have generated layout
18
, the designer may again use simulation and verification tools
11
to verify the behavior of the circuit based on the more accurate layout level netlist
22
before sending the completed IC layout
18
to an IC manufacturer.
Placement and Routing
FIG. 2
illustrates a typical example of an iterative placement and routing process carried out at step
16
of FIG.
1
. The designer may initially create a floor plan (step
24
) for the layout when particular areas of the semiconductor substrate are to be reserved for particular cells. A P&R tool then develops a placement plan (step
26
) indicating where each cell referenced by gate level netlist
14
is to be placed and how it is to be oriented within a semiconductor substrate in a manner consistent with the floor plan. Thereafter the P&R tool develops a routing plan (step
28
) describing the paths followed by the nets interconnecting cell terminals. The placement and routing steps
26
and
28
are iterative in that when the P&R tool is unable to develop a routing plan at step
28
providing a suitable route for every net of the design, it returns to step
26
to reposition the cells and then attempts to develop a suitable routing plan for the altered placement plan at step
28
.
Within most digital ICs, signals pass between blocks of logic through clocked devices such as registers and flip-flops so that the clock signals clocking those devices can synchronize the timing with which the logic blocks pass signals to one another. The logic blocks are therefore subject to timing constraints in that they must be able to process their input signals to produce their output signals within the period between clock signal edges. The time required for a logic block to process its input signals is a function of the processing speed of each cell within the logic block involved in the signal processing, and is also a function of the signal path delays through the various nets interconnecting those cells. Although the placement and routing tools may find space in the layout for all cells and for all of the nets interconnecting them at steps
26
and
28
, the path delays through some of the logic blocks may fail to meet timing constraints.
Thus after the P&R tools have established placement and routing plans at steps
26
and
28
, it is necessary to verify that all logic blocks meet their timing constraints. To do so, an “RC extraction tool” initially processes routing plan (step
30
) to determine resistances and capacitances of the various sections of nets described by the routing plan and passes that information to a timing analysis tool. Since the path delay through a net is a function of its resistance and capacitance (path inductance is usually neglected) the timing analysis tool (at step
32
) is able to compute path delays through the various nets based on the resistance and capacitance information provided by the RC extraction tool. The timing analysis tool also consults the cell library to determine the path delay through each cell of interest.
Based on the information provided by the timing analysis tool, the placement and routing plans are subjected to an “in place optimization” process (step
34
) in which the path delays through the various logic blocks are analyzed to determine whether they meet their timing constraints. When a logic block fails to meet a timing constraint, the placement plan can be incrementally modified (step
35
) by inserting buffers in signal paths to reduce path delays or by moving cells of the logic block closer together or resizing cells to reduce path delays between the cells. The routing plan is then altered (step
28
) as necessary to accommodate the altered placement plan. The RC extraction process (step
30
) and the timing analysis process (step
32
) may also be repeated. The process iterates through steps
28
,
30
,
32
,
34
and
35
until placement and routing plans satisfying all timing constraints are established.
The layout process may also include a step of checking the layout for various signal integrity problems (step
36
) including, for example, static timing analysis and cross-talk analysis, and may iteratively modify the placement and routing plans at step
35
to resolve these problems.
A clock tree synthesis tool may also be employed to design one or more clock trees (step
37
) for the IC. A clock tree is a network of buffers for distributing a clock signal to the various registers, flip-flops and other clocked circuit devices. The clock tree design specifies a position for each buffer forming the clock tree and the routing paths interconnecting the buffers that will ensure that each clock signal edge arrives all clocked devices at substantially the same time. After the clock tree has been designed, the placement and routing plans are modified (steps
35
and
28
) as necessary to incorporate the buffers and nets forming the clock tree into the layout.
A power analysis step
39
may also be carried out in which the layout is analyzed to dete
Bedell Daniel J.
Cadence Design Systems Inc.
Garbowski Leigh M.
Rossoshek Helen
Smith-Hill and Bedell
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