Quad state memory design methods, circuits, and systems

Details Quad state memory design methods, circuits, and systems Quad state memory design methods, circuits, and systems

2001-01-22

2004-01-13

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ternary

C365S154000, C365S233100

Reexamination Certificate

active

06678188

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to electronic circuit design and particularly relates to the design methods of a quad state memory and the related circuits and systems.
(2) Description of the Related Art
Memories or flip flops used to design today's integrated circuits are based on storing one of two logic states, a first state for indicating a logic one and a second state for indicating a logic zero. Stored logic states are transferred between two-state memories either directly or via Boolean logic gates located between the memories. The transfer of two-state logic signals requires a wire for each unique signal transferred. Moore's Law predicts that the number of transistors per square inch on integrated circuits doubles each 18 months. Thus, potentially the number of two-state memories and signaling wires double each 18 months. As the density of integrated circuits tracks Moore's Law, the wiring within integrated circuit emerges as a serious obstacle to the advancement of semiconductors. Also, as the number of signaling wires increase, power consumption of integrated circuits, related to charging and discharging of wiring capacitance, also increases and emerges as another serious obstacle to the advancement of semiconductors. Lowering integrated circuit operation speed can reduce power consumption, but at the expense of performance. Lowering integrated circuit operating voltages can reduce power consumption, but the electrical properties of semiconductor material will eventually arrive at a point to where further reductions in operating voltages is not a possibility. Therefore, a need has arisen in the industry for a new approach in designing integrated circuits such that it is possible to maintain the ability to include more and more functionality within an integrated circuit.
BRIEF SUMMARY OF THE INVENTION
The present invention provides novel quad-state memory and other circuit elements that can be used as fundamental building blocks for designing high speed, high density, and low power integrated circuits. The quad state building block elements enable integrated circuits to operate using fewer wiring interconnects as compared with integrated circuits designed with conventional two state building block elements. Advantageously, even though fewer wiring interconnects are used, integrated circuits designed using the quad state building block elements of the invention maintain the signaling speed and information density of integrated circuits designed with conventional two state building block elements. The quad state building block elements include both elements for storing quad state signals and for performing logical operations on quad state signals. The present invention provides for interfacing between quad state and two state circuit domains to enable both technology domains to be used together on the same integrated circuit. The present invention provides for testing of quad state circuit elements used within an integrated circuit. Further, the present invention provides for inputs and outputs of integrated circuit to operate using the quad state signaling approach, which allows a reducing the number of input and output terminals required on an integrated circuit.


REFERENCES:
patent: 6181603 (2001-01-01), Jyouno et al.
patent: 6215728 (2001-04-01), Yamada

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