Quad SRAM based one time programmable memory

Details Quad SRAM based one time programmable memory Quad SRAM based one time programmable memory

2009-09-28

2011-10-18

Dinh, Son T (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having fuse element

C365S189050, C365S189110

Reexamination Certificate

active

08040748

ABSTRACT:
A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse.

REFERENCES:
patent: 5467304 (1995-11-01), Uchida et al.
patent: 7098721 (2006-08-01), Ouellette et al.
patent: 7154800 (2006-12-01), Imondi

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