Quad pumped bus architecture and protocol

Details Quad pumped bus architecture and protocol Quad pumped bus architecture and protocol

2001-08-10

2003-07-29

Myers, Paul R. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

Reexamination Certificate

active

06601121

ABSTRACT:

FIELD
The invention generally relates to processors and in particular to a quad pumped bus architecture and protocol.
BACKGROUND
With the increasing complexity and demands of today's software and applications, there is demand for processors to provide increased throughput and bandwidth. There may be one or more resources which can operate to limit computer performance, such as input/output (I/O) speed or bandwidth, memory size, etc. One resource that usually limits or throttles computer performance is the speed and bandwidth of the processor bus or front side bus, which is the bus provided between one or more processors and the chipset. For example, some Pentium® processors (such as a Pentium Pro® processor by Intel Corporation) include a 64 bit data bus and can transfer 8 bytes per processor clock cycle, and can transfer a 32 byte cache line in 4 clock cycles. Thus, if the processor clock is provided at 100 MHz (as an example), the data transfer rate would be 800 Mbytes per second. Various details of the Pentium Pro processor architecture can be found in the “Pentium Pro Family Developer's Manual, Volume 1: Specifications,” January, 1996, ISBN 1-55512-259-0. While a data transfer rate of 800 Mbytes per second is sufficient for many applications, a need exists for a processor bus that provides an improved data transfer rate or bandwidth.
SUMMARY
According to an embodiment of the present invention, a method of transmitting information over a multidrop bus from a driving agent to one or more receiving agents is provided. A common bus clock is provided to both the driving agent and the receiving agent. A bus transaction is issued from the driving agent to the one or more receiving agents, including: 1) the driving agent driving multiple information elements for a request onto an address bus at a rate that is a multiple of the frequency of the bus clock; and 2) the driving agent activating a first strobe signal to identify when the receiving agent should sample the information elements driven on the address bus. The method also includes transferring data from the driving agent to the one or more receiving agents including: 1) the driving agent driving multiple information elements onto a data bus at a rate that is a different multiple of the frequency of the bus clock; and 2) the driving agent activating a second strobe to identify when the one or more receiving agents should sample the information elements driven onto the data bus.


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