Quad flat non-leaded chip package

Details Quad flat non-leaded chip package Quad flat non-leaded chip package

2008-08-29

2010-12-14

Clark, Jasmine J (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

On insulating carrier other than a printed circuit board

C257S701000, C257S702000, C257S782000, C257S783000, C257S784000, C257S787000, C257SE23034, C257SE23036, C257SE23039

Reexamination Certificate

active

07851896

ABSTRACT:
A Quad Flat Non-leaded (QFN) chip package including a patterned conductive layer, a first solder resist layer, a chip, a plurality of bonding wires and a molding compound is provided. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface, wherein a part of the first surface is exposed by the first solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the first solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the chip and the bonding wires.

REFERENCES:
patent: 6429508 (2002-08-01), Gang
patent: 6528722 (2003-03-01), Huang et al.
patent: 6531770 (2003-03-01), Nakashima
patent: 6787915 (2004-09-01), Uchida et al.
patent: 6858919 (2005-02-01), Seo et al.
patent: 7436074 (2008-10-01), Pan et al.
U.S. Office Action of U.S. Appl. No. 12/196,791, dated Jul. 30, 2009.

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